Lab 4 - ECE 421L 

Authored by Benjamin Molina, molinb1@unlv.nevada.edu

9/26/2023

Prelab:

The prelab for this lab involved backing up previous work and going through Tutorial 2. Which we will quickly show below. 

Tutorial 2 has us focusing on creating the layout of an NMOS and a PMOS  and then using LVS to see if it matches the schematic of NMOS and PMOS. 

For the NMOS:

Below we have the layout of the final NMOS layout design, the curves generated from the schematic and the IV curves generated from the extracted view of the NMOS design.

For the PMOS:

Similar to the NMOS we have the layout view, the IV curves given by the schematic and then the simulation that uses the extracted view rather than the schematic. If done correctly they should match.

Lab description:

The first step we are to perform is to produce 4 simulations 2 per device. For the NMOS a 6u/600n ratio must be used and for the PMOS device a 12u/600n ratio will be assumed. 

Simulation #1: ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.

Simulation #2: ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.

Simulation 3: ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. 

Simulation #4: ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.

The next step we must perform will involve creating a layout with these NMOS and PMOS devices and combining them with a probe pad which are smaller than probe pads. Be sure to look at MOSIS if you are confused about the design rules for these pads. All they are, is a simple "glass" layer over a bigger "metal3" layer.

NMOS:

Below we see the layout created with the pads and the NMOS that is based on the examples provived by Dr. Baker, as always we DRC this design to make sure all is in order and spaced out evenly. When you get zero errors extracted this layout for later use.

We now make a schematic with the probe pad symbols for the NMOS noting that the Body pin that we normally use is simply gnd!.

Then all we need do is LVS using the schematic and the extracted view we made earlier. Here we can see that the netlists match and I have included a zoomed in view of the NMOS device and how it is connected to the pads.

PMOS:

Just as before with the NMOS we now must do the same thing with teh 12u/600n PMOS that we have built. Once again using DRC to check when we finish designing. Extract when given zero errors.

The schematic for the PMOS design this time using the Body pin and connecting it.

And finally we LVS the schematic and the extracted view and if done correctly the two netlists must match. Once again for convience I have zoomed in on the PMOS device to show how it connected to the pads in the layout. 

Proof of backing up and saving work:

Work was zipped and sent to google drive as a backup and extra save.

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