Lab 5 - ECE 421L 

Authored by Matthew Lord, lordm1@unlv.nevada.edu

October 11th, 2023

 

Prelab:


Going Through Tutorial 3
        In its entirety, tutorial 3 takes us through:

o   Design of schematic inverter

o   Creating symbol view of inverter

o   Layout of inverter

o   Simulation of inverter schematic

Below is my symbol and schematic for tutorial 3.

Here is my Layout showing a good LVS for tutorial 3.

Lab Report:


Zipped files per the instructions

12u/6u Inverter (Width of PMOS / Width of NMOS)

Symbol for my 12u/6u inverter.

 

Layout showing good LVS of my 12u/6u inverter.

Simulations using Spectre.


Simulations using Ultrasim.


We can observe from the previous simulations that as the capacitive load increases, the time it takes for the inverter to respond to the input signal increases as well.

48u/24u Inverter (Width of PMOS / Width of NMOS)

Symbol for my 48u/24u inverter.

 

Layout showing good LVS of my 48u/24u inverter.

Simulations using Spectre.

Simulations using Ultrasim.

We can observe from the simulations that the four finger inverter performs better because the additional fingers or branches of the MOSFET allow the capacitor to more efficiently charge and discharge.


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