Lab 4

Lab 4 - ECE 421L

Authored by Matthew Lord, lordm1@unlv.nevada.edu

September 27th, 2023

Prelab:

I use a RAID 1 config on my main computer with the important files being backed up to my cloud, along with a second computer in my livingroom that downloads any changes to my files in the cloud, so all in all I have 2 physical locations using RAID 1 along with my cloud backup

Below is my layout from tutorial 2 for the NMOS device.

This is the schematic from tutorial 2 for the NMOS device.

Below is my layout from tutorial 2 for the PMOS device.

This is the schematic from tutorial 2 for the PMOS device.

Lab Report:

Creating Schematics/Symbol Views for NMOS/PMOS

Before beginning simulations, we needed to create schematics and symbols for the transistors that we would be using.

NMOS Schematic and Symbol

PMOS Schematic and Symbol

I_D v. V_GS of NMOS Device

· In the first simulation, we let V_DS vary from 0 to 5V in 1mV steps, and we sweep V_GS from 0 to 5V in 1V steps.

· We also set the length of the NMOS to 600 nm, and the width to 6 microns.

Shown below are the schematic and the IV curves of this NMOS with the given parameters.

I_D v. V_GS of NMOS Device

· In the second simulation, we set V_DS at a constant value of 100mV, and we sweep V_GS from 0 to 2V in 1mV steps.

· We keep the same length and width of our MOSFET, and instead of simulating I_D v. V_DS as we did previously, we simulate I_D v. V_GS.

The schematic and IV curves are shown below.

I_D v. V_SG of PMOS Device

· The third simulation calls for a sweep of VSG from 0 to 5V in 1V steps, and VSD should vary from 0 to 5V in 1 mV steps.

· The width of the PMOS is changed to 12 microns, while the length is kept at 600 nm.

· Note that the base of the PMOS is tied to VDD in this schematic. In the NMOS schematics, the base was tied to ground.

Below are the schematic and the IV curves for the PMOS device.

I_D v. V_SG of PMOS Device

For the final simulation, we set VSD to 100 mV and we sweep VSG from 0 to 2V in 1 mV steps.

Using the same width and length of the previous MOSFET, we observe the results below.

Layout of 6.0u/0.6u NMOS Device

Full Layout of NMOS Including Probe Pads with DRC.

Zoomed-In View of Layout of NMOS Device & LVS Verification

Layout of 12.0u/0.6u PMOS Device

Full Layout of PMOS Including Probe Pads with DRC.

Zoomed-In View of Layout of PMOS Device & LVS Verification