Lab 3 - ECE 421L 

Authored by Matthew Lord, lordm1@unlv.nevada.edu

September 20th, 2023

 

The purpose of Lab 3 is to layout the 10-bit DAC that was designed in Lab 2.

Prelab:

I use a RAID 1 config on my main computer with the important files being backed up to my cloud, along with a second computer in my livingroom that downloads any changes to my files in the cloud, so all in all I have 2 physical locations using RAID 1 along with my cloud backup.

Below you can see the layout used for tutorial 1 and the DRC.

As seen below I successfully completed tutorial 1 with the netlists matching after running the LVS on my R_div.


Lab:

I started this lab by copying in some of my files from lab 2 that would be used for this lab.

The coponent we would need to create was a 10k resistor using the equations below to find the dimensions needed.

       

R = Rd * (L/W)

         

R = 10k Ω

Rd = 800

W = 4.5 microns

       

10k = 800 * (L/4.5 microns)

L = 56.25 microns (due to the pins skewing the resistance the length I ended up needing was 55.8)

      

To accomplish the needed resistance I used 55.8 microns by 4.5 microns.

Below is a picture of the resistor with a ruler showing measurements used as well as a DRC of the layout.



Below is the extracted view of the layout to show the calculated resistance of approximately 10K


First I made a 1 bit layout to verify it against the components used in the schematic and simplify the creation of the 10bit DAC layout.


I know that my single bit components passed the LVS, so im ready to assemble the 10bit DAC.


Below is the layout using my single bit components I tested earlier.


Here is a close up of my B0 input and the extra 10K connected to ground.

 
Here is a close up of my B9 input and our Vout pin.


This is the schematic that well be testing out layout aganist.


And here we have the successful LVS result for the 10bit DAC.


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