Lab

Lab 1 - EE 421L

Authored by Anthony Lopez

Email: lopeza78@unlv.nevada.edu

Due Date: September 13, 2023

Lab Description:

Pre-Lab:

Files

For this lab we need to download and define a lab2 file which contains the ideal 10-bit ADC and DAC. We just download the zip file and uplaoad to our cmos directory and then unzip its contents once that is done and you defne it in our cds.lib we see the following.

Simulation

Now with the proper files in our library we will load and sumulate the sim_Ideal_ADC_DAC schematic.

- Schematic of the previously mentioned file

-Here is the generated graph from our simulation.

How it works

Now we can discuss how the DAC and the ADC work. From right to left on the schematic you see an input signal vin go into our ADC then output nine bits to help try to map out this signal in steps through the bits. Thats why our v out signal is in a more step looking wave form. The DAC takes in those output bits form the ADC to then display it in an anolog form again but now through the steps of the bits given. Since we have an 10 bit ADC our wave form has around 10 steps from low to high or high to low.

Now to find the least significant bit, you derive it through the following equation

                        LSB = VDD/2^N
                        - VDD is your reference signal/voltage and N is your number of bits.
                        - Thus we have a VDD of 5v and our 10 bit system then your LSB = 5v/2^10 which is 4.88mV.
                        -This is the amount of voltage change your circuit needed to change your bit value.

Another example

Here we have an input wave whose amplitude was changed to 10mv with an offset of 20mv. Thus its peaks are 30mV to 10mv.

- Here you can see that there are 4 steps to each peak. This is due to the fact that the peaks are about 4 LSBs of voltage from each other. From the equation we saw that our LSB is 4.88mv or about 5mv thus our difference of 20 mv from peak to peak divided by 5mv is 4. 20mv/5mv = 4. Showing that our bit value changes, ie creates a new step at each added 5mv.

Lab Tasks:

Desiging thr DAC

To make the process of creating our DAC symbol easier, we start with just a voltage divider which then turns into the symbol below the schematic.

Since each symbol in a way represents one bit for our DAC we then make 10 in series to simulate the outline of the given figure 30.14. This gives the following schematic

Now we can make our final DAC symbol

Output Resistance

The following is my work to show how I found the output resistance to be Ohms.

Delay, driving a load

This is my hand calculation of the DAC delay usinf 0.7RC

Here we ground all DAC inputs except B9. Connect B9 to a pulse source (0 to VDD)

- Here we see the simulation validates my hand calculation.

Return