Lab 5 - ECE 421L 

Authored by Kanoa Hokoana, hokoana@unlv.nevada.edu

October 4, 2023

Lab 5: Design, layout, and simulation of a CMOS inverter

For the prelab I went through tutorial 3.

For tutorial 3 I made an inverter. This is the schematic for the inverter.

I then made a symbol.

I then made another schematic with the symbol.

Then I made a layout for the inverter.

DRC and LVS check

I then simulated the inverter.

This concludes tutorial 3 and the prelab.

For the main part of the lab I drafted and simulated two inverters. One 12u/6u  and one 48u/24u.

This is the schematic for the 12u/6u inverter.

I then made the symbol for the schematic.

Then I made the layout for the 12u/6u inverter.

DRC and LVS Check

I then simulated the 12u/6u inverter driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load.

Spectre

Ultrasim

I then drafted the schematic for 48u/24u inverter.

I then created a symbol for the 48u/24u inverter.

I then drafted the layout for the 48u/24u inverter.

DRC and LVS Check

I then simulated the 48u/24u inverter driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load.

Spectre

Ultrasim

These are the files used in this lab: lab5_new.zip

Backing up my work

This completes lab 5.

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