Lab 5 - ECE 421L 

Authored by Kyle Abenojar, abenok1@unlv.nevada.edu

October 11th, 2023

 


Prelab:

For lab 5, we were tasked with completing Tutorial 3 for our prelab.
   
The first step is create a new schematic titled "inverter".
Pic1
   
We can then open up our previous NMOS and PMOS schematics and copy and paste our NMOS and PMOS cells onto our new inverter schematic.
Pic2
Pic3
   
Next, I added vdd and ground to my schematic as well as pins for A (input) and Ai (output) then wired them all together to get the following.
Pic4
   
After DRCing my schematic and ensuring there are no errors, I then created a symbol for my inverter
Pic5
   
After ensuring there were no errors with my symbol, I then created a new layout view for my inverter and placed a PMOS, NMOS, ptap, ntap and m1_poly to get the following
Pic6
   
I then added metal to connect the drains of the PMOS and NMOS. I also added metal to connect the source of the NMOS to ground and to connect the source of the PMOS to vdd. I also added poly to connect the gates of the NMOS and the PMOS. Lastly, I added pins for my input A, output Ai, vdd! and gnd!.
Pic7
   
After this, I extracted my layout to get the following. I also performed an LVS to ensure that my netlists matched.
Pic8
Pic9
   
Next, I created a new schematic to simulate my inverter.
Pic10
   
Using my inverter symbol, I generated the following schematic.
Pic11
   
After launching the ADE L, I changed the model library to include the proper files.
Pic12
   
I then setup a dc analysis using the following parameters.
Pic13
   
After choosing my outputs to chart, my window looked like the following.
Pic14
   
I then ran my simulation however, as we can see, our results aren't what we expected. That's becuase we didn't include vdd in our simulation.
Pic15
   
First, we go back to our schematic and add vdd.
Pic16
   
Then, back in the ADE L, we set up vdd as an analog stimuli at 5V.
Pic17
   
Now, when we simulate our device, we get the proper input and output.
Pic18
   
Next, we simulate our extracted schematic and as expected, we get the same graph.
Pic19

Lab Report:
For the first part of this lab, I used the 12u/6u inverter that we created during the prelab while performing Tutorial 3. Below are the schematic, symbol, layout, extracted view, and LVS Results.
Pic20
Pic21
Pic22
Pic26
Pic27
     
The next step in this lab was create a 48u/24u CMOS inverter. Below
are the schematic, symbol, layout, extracted view, and LVS Results.
Pic23
Pic24
Pic25
Pic28
Pic29
   
After creating our inverters, we were tasked with simulating the operation of each of them driving a 100 fF, 1pF, 10pF and 100 pF capacitive load. We simulated each circuit twice, once using a transient analysis with Spectre and another time using a transient analysis with Ultrasim, Cadence's fast SPICE simulator. Below, I will label each circuit and paste both the transient analysis using Spectre (left picture) and tran analysis using UltraSim (right picture).
   
12u/6u with a 100 fF load:
Pic30
Pic31 Pic 46

12u/6u with a 1 pF load:
Pic32
Pic33 Pic477
     
12u/6u with a 10 pF load:
Pic34
Pic35   Pic48
   
12u/6u with a 100 pF load:
Pic36
Pic37  Pic49
     
48u/24u with a 100 fF load:
Pic38
Pic39  Pic50
     
48u/24u with a 1 pF load:
Pic40
Pic41  Pic51
   
48u/24u with a 10 pF load:
Pic42
Pic43   Pic52
     
48u/24u with a 100 pF load:
Pic45
Pic45  Pic53
   
As we can see from our results, our inverter works as we expected. When the input is 0V, our output is 5V and vice versa. We also see that there is a delay for the output to reach its final state. With increasing capacitive load, we see that the delay increases. With the 48u/24u, we see that the transition happens faster because the larger CMOS inverter has a decreased resistance. We also see slight variations between our outputs from the Spectre and UltraSim SPICE models. As we know, UltraSim is faster but at the cost of accuracy so we know that our Spectre simulations are closer to real operation.

Zip File Containing CMOS Inverters and Simulation Circuit:
lab5.zip

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