Lab 2 - ECE 421L
Authored
by: Cesar Nieves
Today's
date: September 1, 2021
Email: nievec2@unlv.nevada.edu
Lab
description:
- In this lab we are introduced to a design of a 10-bit dgital-to-analog conveter and how to understand it.
Pre-Lab:
- First, we must download the lab2.zip provided and upload that zip file into our Cadence account.
- Then we would unzip the file in the CMOSedu directory and add in cds.lib "DEFINE lab2 $HOME/CMOSedu/lab2".
- Open Cadence > lab2 > sim_Ideal_ADC_DAC to open the schematic and run it like in lab 1.
schematic
data
- Finally,
we had to make sure we knew what we are looking at and explain how the
input voltage, is related to b [9:0] and output voltage.
Lab:
First,
we are going to create a voltage divider. Which is just two resistors
in series with another resistor in parallel. Then we create that into a
symbol (below).
Schematic
Symbol
After creating that symbol, we are going to make a 10 digital-to-analog conveter out of it (below).
Full Schematic
Close up
Then we are going to make that schematic into a symbol.
After we are going to test the time delay. We know that the
time delay in this circuit we need the equivalent resistance and the
load capacitance.
time delay = .7*R*C = .7*10k*10p = 70 ns
Hand Calculator
Below is the data from my 10 bit DAC, showing that the time delay is about 70 ns.
For
the schematic called "sim_Ideal_ADC_DAC" we are going to take away the
DAC element it has and replace it with the one I created with the data
from it.
Schematic with my 10 DAC
Schematic with the data
New schematic with the load being 10 k resistance and its data
Schematic with my 10 DAC
Schematic with the data
New schematic with the load being 10 p capacitance and its data
Schematic with my 10 DAC
Schematic with the data
New schematic with a load of 10 k resistance in parallel with 10 p capacitance and its data
Schematic with my 10 DAC
Schematic with the data
Return