Lab 3 - Layout of a 10-bit digital-to-analog converter(DAC) ECE 421L 

Authored by Luis Garcia Rivas,

garciari@unlv.nevada.edu

September 13, 2021

  

Prelab

For my prelab I was tasked with completing tutorial 1 which is a tutorial that explains the process of creating a layout of a circuit using n-well resistors.

I've already completed this tutorial previously for my lecture so I've used the same the screenshots. Only difference is the lecture was a 1/4 Divider instead of 1/2.

Base Pre Schematic

(Schematic of 1/4 Divider)

4 10k nwell layout

(Layout of 1/4 Voltage Divider using 10k n-well resistors)

 Lab

1Base Divider for 10BitDac
The first step of this lab was to create the base schematic for designing a 10bit DAC. I achieved this by creating a schematic that contains 1 input 2 input/output pins.
This schematic provides the basis for our DAC and allows for a simplified design. We will use this design 10 times in our DAC once per bit. After completing schematic
I drc'd to ensure that no errors were made.
DRC Splitter
Symbol
After designing I created a symbol so that we can move onto connecting all of these symbols and creating my DAC.
210BitDac
In this step I had to use my previously created symbol to create my 10 Bit Dac. I copied the already existing 10 bit DAC design
so that I wouldn't have to edit symbol size to get it to fit in the ADC to DAC schematic. After implementing my symbols for each
bit I next had to add an additional resistor in bit 0 as well as a ground. After completing this schematic I drc'd the schematic to
ensure no errors were made.
3Testing DAC
After successfully creating 10 Bit DAC I next extracted the symbol for my 10 Bit DAC and then ran a simulation using my DAC to make sure that my design worked.
It did.
Transisent Analysis
410k nwell
Since everything worked well I can now move on to creating the layout of my 10 Bit DAC. I first had to create a 10k n-well. After creating the layout for my 10k nwell
I had to extract the layout to ensure my design was correct and indeed did have 10k resistance.
10K Extracted
5splitter layout
After successfully laying out my 10k n-well resistor I next moved onto laying out my bit symbol. This was achived by stacking 3 resistors on top of each other. The first
resistor takes in the bit controller input, the second resistor functions as the resistor in series with the input resistor and the third resistor takes in the input from a lower level.
I also added 3 pins an in, bot, and top bit.
6DAC Layout
After laying out the bit resistors I could finally move onto laying out my 10 bit DAC. This was simple since I designed my 10 bit dac in modules so all I had to do was
instantiate 10 of the bit layouts and connect them in the right manner. An additional step I had to perform was adding pins for the inputs that denote which bit is coming
into my resistor. Before I began to layout my bit layouts I had to make sure that were layed out in an ordered manner. To ensure this I had denoted a constant x-position
as well as how much lower each next bit should be. I decided that each bit layout should be 45um apart from each other.(Measured from the origin of each layout) I drc'd
my layout to make sure that no spacing errors were made or no loose metal connections existed.
Layout DRC
After orderly laying out my bit layouts and making all the right connections all that was left to do is test the LVS.
LVS
LVS passed successfully and I had successfully layed out my 10 Bit Dac.

FinalDesign.zip

User created cells 10KNwell,Splitter,MYDesign_10-bit_DAC, & sim2_IDEAL_ADC_DAC

 

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