Lab 7 - Using buses and arrays in design of word inverters muxes, and high speed aadders ECE 421L 

Authored by Luis Garcia Rivas,

garciari@unlv.nevada.edu

November  3, 2021

Prelab

1	First inverter All 31 Inverters For the prelab I was tasked with completing tutorial 5 which explains the concept of buses and arrays within cadence. The tutorial walks through creating a ring oscillator schematic, symbol and layout in order to explain buses and arrays. The first step of the prelab is to create the schematic of a 31 stage ring oscillator which is done by creating a string of 31 inverters each one feeding into the next.
2	After creating the schematic I ran a simulation of the schematic to see the output of the 31 stage ring oscillator.
3	Next the tutorial explains a more concise and neater way of creating the same schematic but this time with the use of arrays and buses we're able to perform the same function but only using 1 symbol view of an inverter. This is done by editing the symbol values to tell cadence that we're actually using 31 inverters. This was done by putting an array next to the instance name(I0 <30:0>). After editing the symbol value I next had to use buses since we now how 31 instances of the inverter thus we needed 31 different inputs and outputs. However since the final output feeds back into the first input we had to make cadence aware of this. I did this by naming the final output a different name so that cadence knows the last stage of the oscillator ring feeds back into the first inverter.
4	The next step is to layout the 31 ring oscillator. I was initially scared about performing this step since it means 31 different inverters however the tutorial showed me that I didn't have to layout 31 different inverters not even just 1 inverter. Instead I used my already created inverter from previous labs then added metal 1 extensions to extend my Ai(output of inverter), VDD and GND. After doing this I copied this inverter and inputted that I would be copying it 30 times. After laying out all 31 stages I next had to make a metal 2 connection from the 1st stage input to the 31st stage output to feedback stage 31 to stage 1. Thus I was able to layout the 31 stage ring oscillator in minutes.
5	Extracted View Edited schematic After laying out I next extracted my layout then ran an LVS which failed. It failed because the 31st stage set as an output in my layout but not in my schematic to fix this I edited my schematic by adding an output pin to the last stage so that we not only feedback the final output but also output it. With this modification I was now able to pass LVS.
6	After passing LVS all that was left to do was simulate our schematic to make sure it works as intended by using the extracted netlist. It simulates the same thus I succeeded. However to make sure it was infact using the extracted view for simulation I outputted the netlist and it shows that it was simulating using the extracted view.

 Lab

Part 1: 4 Stage Inverter

1	For the first part of Lab 7 we essentially do the prelab again except with no layout and only using 4 stage inverter. Again we create a 4 stage inverter except we now use our newly gained knowledge of buses and arrays to only have to use 1 inverter symbol.
2	After creating the schematic I created a symbol for the new inverter. I created symbol since this is no longer a basic inverter but now a 4 stage inverter.
3	After creating the symbol I next moved onto creating a new schematic for the purposing of simulating the 4 stage inverter to make sure it was properly created and working as intended. I only used a capacitor for 3 of the stages because I wanted to show the influence of a capacitor on the delay of the output.
4	Finally I simed the schematic. As anticipated the inclusion of capacitors introduced a delay. This delay is varied between the outputs that have capacitors(out<3>,out<2>,out<1>) since output has a different capacitor value. Out<3> has the least amount of delay since it has the smallest capacitor and out<1> has the highest delay since it has the largest capacitor. Out<0> has essentially no delay since it has no capcitor to output to.

Part 2: 8 bit Inverter

1	This again another repeat of the prelab and lab part 1 but this time we're creating an 8 bit inverter. We repeat the same steps, we create a schematic but denote that its 1 inverter symbol with 8 bits.
2	After creating the schematic I next created a symbol for my 8 bit inverter to denote it has 8 bits.
3	After creating the symbol I next create a sim schematic using the symbol to ensure our 8 bit inverter works as intended. After simming I can confirm that my inverter works as intended.

Part 3: 8 Bit And

1	The next part of the lab involved the creation of an 8 bit AND gate. Like previous parts we start by using a 1 bit AND gate and through the use of buses and arrays turn it into an 8 bit array.
2	After checking and saving the schematic I next moved onto creating the symbol for our 8 bit AND gate.
3	I next created the schematic for simming and then simmed the schematic to test out my 8 bit AND gate.

Part 4: 8 Bit NAND Gate

1	For part 4 we repeat Part 3 but instead of using an AND gate I used an NAND gate. I started out by creating a schematic using a 1 bit NAND gate then converted it to an 8 bit NAND gate.
2	My schematic successfully checked and saved thus I was able to move onto the next step which is creating a symbol for my 8 bit NAND gate.
3	Finally I moved onto simming my symbol to ensure that it works properly.

Part 5: 8 Bit NOR Gate

1	For part 5 we repeat the last part but unlike the last part in this part we will be converting a 1 bit NOR gate to an 8 bit NOR gate. Like the previous part start by using our 1 bit NOR gate and convert it to an 8 Bit NOR gate through the use of buses and arrays.
2	After checking and saving our design I could next move onto creating a symbol for my 8 bit NOR gate.
3	After successfully creating my symbol I could finally move onto testing out my schematic to ensure that it works as intended.

Part 6: 8 Bit OR Gate

1	I started out by creating a schematic using my OR gate and modify it to convert it to an 8 Bit OR gate.
2	After checking and saving my schematic I next moved onto creating a symbol for my 8 Bit OR gate.
3	I next moved onto creating a schematic using my symbol and testing it to make sure that it works as intended.

Part 7: 2 to 1 MUX/DEMUX

1	For part 7 of the Lab I was tasked with creating a 2 to 1 MUX/DEMUX gate then simming it to show how it works as well as show how it could be used as either a MUX or DEMUX. I start out by creating my schematic of a 2 to 1 MUX/DEMUX
2	I next created a symbol for my schematic.
3	I next created a schematic using my symbol to test my schematic works as intended as well as to run multiple simulations to improve understanding of the gate and understand how it can function as both a MUX and a DEMUX. With B set to 0 and A set to 5V we can see that our schematic works by deciding between the 2 inputs A and B through the use of the select line S. S = 0 selects A and S = 1 selects B. After selecting the input my schematic next gives the selected input to our output and outputs the selected input. By switching the outputs and inputs around as well as using SI as the select and S as the inverted select line we can repurpose the same schematic as a DEMUX that instead of selecting 1 of 2 inputs it selects 1 of 2 outputs.

Part 8: 8 Bit 2 to 1 MUX/DEMUX

1	For part 8 of the lab I was tasked with converting the previously made 2 to 1 MUX/DEMUX and converting it to an 8 bit 2 to 1 MUX/DEMUX. To begin we have to create a new schematic in order to add the inversion for input SI inside the schematic and not have an additional input for SI.  This was done by using my previously created inverter and attaching it to the select line input.
2	I next created a symbol for my new 2 to 1 MUX/DEMUX. As we can see with my changes we now have 1 less pin on our symbol.
3	I could finally move onto converting my 1 bit 2 to 1 MUX/DEMUX and turning it to an 8 bit 2 to 1 MUX/DEMUX. This is done by creating a schematic using my 1 bit symbol and using buses and arrays to convert it to an 8 bit 2 to 1 MUX/DEMUX.
4	I next created a symbol for my 8 bit 2 to 1 mux.
5	I next moved onto simming my symbol to ensure that it works properly.

Part 9: Full Adder

1	COUT Section of Full Adder SUM Section of Full Adder For part 9 I was tasked with creating a Full Adder. I first started by creating a schematic for a full adder using Fig 12.20 as a guide.
2	After creating my schematic I next moved onto creating a symbol for my full adder.
3	I next moved onto simmulating my symbol to ensure that my schematic works as intended.
5	Despite not being told I dedcided to layout my 1 bit full adder to save myself trouble when it comes to laying out the 8 bit full adder. I created my layout and DRC'd my design.
6	I next extracted my design and LVS'd my design to ensure that I properly layed it out.

Part 10: 8 Bit Full Adder

1	For part 10 I was tasked with using the previously created full adder to create an 8 Bit full adder. I did this by first creating a schematic using the symbol of the 1 bit full adder I created then modifying it to become an 8 bit full adder. One big difference in this conversion compared to other logic gates is the fact that only the first cin is an input the rest of the cins are the couts of the previous gates feeding into the next. In my schematic I had to denote that only the first cin is actually an input and is the only cin that requires an input pin. I had to the same for the last cout since it doesn't feed into another full adder.
2	After checking and saving my schematic I could next move onto creating a symbol for my 8 BIt full adder.
3	After creating a symbol I moved onto laying out my schematic. This was made easier by having layed out a 1 bit full adder already so all I had to do for layout aside from creating 7 copies is to add metal 1 extensions for VDD and GND as well as connect the couts to the cins of the next full adder. I also had to add input pins for each a and b input and s output. Theres only 1 cin input and 1 cout output so those were the only cin and cout that needed pins the rest I just had to connections to from the previous full adder cout to the next full adder cin. First FA Gate Last FA Gate All 8 FA Gates
4	After laying out my 8 Bit Full Adder and passing DRC I then extracted my design and LVS'd it to ensure our extracted view matched our schematic.
5	After successfully laying out an 8 bit FA I moved onto simulating my 8 Bit FA to ensure it worked as intended.