Lab 7 - EE 421L 

Authored by Charlene Drake

Email: drakec2@unlv.nevada.edu

November 03, 2021

Prelab

For this prelab we were to follow along with Tutorial 5 and design a ring oscillator.

After copying the files from Tutorial 4 into our new library we created the first schematic of the ring oscillator which includeda VDD and 31 inverters that we had created in a previous lab.

With our schematic created and our output wire labeled we were able to run the schematic and received the following simulation.

As you can see our simulation is not looking right so we need to add initial conditions of 0V to the wire labeled osc_out and we receive the folowing simulation.

Not that we know how the simulation should look, we are able to simplify the original schematic by using arrays and busses.

After simulating our new schematic we receive the same waveform like the previous simulation.

Now we are able to create the layout of our ring oscillator by first instantiating two inverters and connecting them at vdd, gnd, and the Ai of the first inverter and A of the second inverter. From there we are able to copy the design and instantiated it 30 more times.

With our layout complete and our design extracted, we can DRC.

When we try to LVS, though, our net-lists fail to match and we need to edit our schematic by adding an output pin label "osc_out."

Now when we LVS everything matches.

Now we can create a symbol for our ring oscillator by copying and pasting the schematic and then deleting VDD.

With that symbol we are able to instantiate a VDD and add a wire labeled osc_out to run another simulation where we receive the same results.

From the extracted cell view of our simulation, we receive the same results, again.

Lab Description

For this lab we were asked to first design a 4-bit inverter, followed by an 8-bit inverter, NAND, NOR, AND, and OR gates.

To start off, we first needed to design an inverter that used 6u/0.6u NMOS and PMOS devices since the one we previously designed used 12u/0.6u.

Now we were ready to carry on with our designs.

4-bit Inverter

Schematic & Symbol:

Simulation Schematic & Simulation:

As you can see, whenever a low input is received, we get a high output and when a high input is received a low output which is just as expected from an inverter. As for the effect of capacitance load on our outputs, we see that with out<0>, which has no capacitance load, is very fast and has less of a rise and fall time. Out<1> has the largest capacitance load and has the slowest rise and fall time. In conclusion, the larger the capacitance load, the longer the delay for the capacitor to charge.

8-bit Inverter

Schematic & Symbol: 

Simulation Schematic & Simulation:

8-bit NAND Gate

Schematic & Symbol:

Simulation Schematic & Simulation:

As you can see, for the inputs "00," "01," & "10" a 1 is output but with the input "11" a 0 is output.

8-bit NOR Gate

Schematic & Symbol:

Simulation Schematic & Simulation:

8-bit AND Gate

Schematic & Simulation

Simulation Schematic & Simulation:

Following the truth table for an AND gate, a 1 is output only from the input "11" while all other inputs receive a 0.

8-bit OR Gate

Schematic & Symbol:

Simulation Schematic & Simulation:

2-1 MUX/DEMUX

Schematic & Symbol:
  

Simulation Schematic & Simulation:


The simulation of our 2-1 mux follows the provided equation Z = A*S + B*Si where whenever a high S input is received, the output follows A and if a low S input is received,  the output follows B.

8-bit 2-1 Mux

Schematic & Symbol:
 

Simulation Schematic & Symbol:


As you can see, our 8-bit 2-1 MUX functions just like the 1-bit 2-1 MUX following the equation

Full Adder

Schematic & Symbol:



Layout & DRC:



Extracted View & LVS:



8-bit Full Adder

Schematic & Symbol:
 

In order to create our layout for the 8-bit full adder, we needed to instantiate our layout of the 1-bit full adder 8 times, connecting each Cout into the next full adder's Cin. The final Cout would then be labeled as Cout<7>.

Layout & DRC:



Extracted  & LVS: