Lab 8

Lab 8 - ECE 421L

Authored by Do Le (led2@unlv.nevada.edu)

Authored by Michael Nguyen (nguyem9@unlv.nevada.edu)

25th of November, 2020

Lab Contributors

Granados Rhyan — granar1@unlv.nevada.edu

• Assisted while drafting lab report.

Le Do — led2@unlv.nevada.edu

• Provided schematics & layouts for:

31-stage ring oscillator with buffer

12µm/6µm inverter

25KΩ N-Well Resistor

Voltage Divider

Lab Project

• Composed top level cell.

• Assisted while drafting lab report.

Nguyen Michael — nguyem9@unlv.nevada.edu

• Provided schematics & layouts for:

6µm/0.6µm NAND & NOR gate

6µm/0.6µm PMOS & NMOS

• Assisted while drafting lab report.

Lab Description

The following lab is about the generation of a test chip used to make real measurements

of IC circuitry. Several circuits and components are implemented in a pad that is

prepared for fabrication. This is a team effort in which Rhyan, Do, and Michael contribute to

parts of the chip.

Prelab

The prelab involves the creation of a 40 pin padframe. The pad frame is made up of 40

75µm x 75µm pads.

The pad consistes of a layer of metal3 with an overglass layer marked above to indicate where the

overglass will be removed during fabrication.

Pad

The pad is then formatted to be fabricated on a 75µm x 75µm chip.

The chip has 40 pins including source and ground and takes a square topology

with 10 pins per side. The following is the schematic for the pad.

BondingPad Schematic

Next is the layout for the bondingpad.

BondingPad Layout

With the bondingpad prepared, an IC circuit is ready to be implemented.

Lab

     During this part of the lab, components are instantiated and added to the bonding pad.
    The goal of this chip is to create test structures to measure the parasitics of C5 components,
    and analyze the operation of circuits fabricated on the chip.

    Our test structures must satisfy the following components list:
    • Course project(s)
    • 31-stage ring oscillator to drive 20pF load
    • NAND and NOR gates
    • Inverter
    • PMOS and NMOS transistors
    • 25KΩ N-Well Resistor
    • Voltage Divider

Pin-Map:
    The following pin map is used to make connections with on-chip components.

Chip Pin #	Pin Description	Comments
1	ocs_out	Ring oscillator output

Chip Pin #	Pins Description	Comments
2	A	Input A
3	B	Input B
4	A NAND B	Output A NAND B

Chip Pin #	Pins Description	Comments
5	A	Input A
6	B	Input B
7	A NOR B	Output A NOR B

Chip Pin #	Pins Description	Comments
8	A	Inverter Input
9	Ai	Inverter Output

Chip Pin #	Pins Description
10	NMOS Gate
11	NMOS Drain
12	NMOS Source

Chip Pin #	Pins Description
13	PMOS Gate
14	PMOS Source
15	PMOS Drain
16	PMOS Body

Chip Pin #	Pins Description
17	Voltage Divider Source
18	Voltage Divider Output

Chip Pin #	Pins Description	Comments
19	NoConn	No Connection
20	Gnd	Ground pin
40	VDD	VDD pin

Chip Pin #	Pins Description	Comments
21	Project V+	Project Postitve Input
22	Project V-	Project Negatitve Input
23	Project Vout	Project Output

Chip Pin #	Pin Description	Comments
25	In+	Positive Input
26	In-	Negative Input
24	Out	Output

Schematic:
    The following is our schematic for the test structures. It shows each pin connection and what components
    they connect to.
Top Schematic

Here is the layout of the chip, all connected to bonding pads.
Top Layout

Layout Detail:
    The following is the design for the 31-stage ring oscillator. The buffer must be powerful enough to drive a
    20pF load, so 4 stages of buffers are created. The final stage buffer has an NMOS and PMOS resistance
    of ~16Ω, so that the delay is about 224ps. The buffer was strong enough to drive the 20pF off-chip load.
RingOscillator Schematic

Here is the layout of the ring-oscillator.
Ring Oscillator Layout

    The following is the voltage divider schematic. The configuration for the test is as followed:
       • Use Pin 17 and Pin 18 to test the 10KΩ resistor.
       • Use Pin 18 and ground (Pin 20) to test the 25KΩ resistor.
       • Apply power to Pin 17 and use Pin 18 to test voltage divider.
VoltageDivider Schematic

Here is the layout for the voltage divider.
VoltageDivider Layout

The following are the layouts for the NMOS and PMOS implemented in the chip.
NMOS

The following are the NAND and NOR gates impelemented in the chip.
NAND

Michael and Do contributed projects to be added for testing. The following is Do's
layout for the project connected to the bonding pad.
Project0 Layout

Here is Michael's layout as seen on the layout view connected to the bonding pad.
Project1 Layout

    The top level cell is then named Chip3_f20, corresponding to our group number.
    Now the design is ready for submission to MOSIS.
    That concludes lab 8.

    The design is available here.
    Chip3_f20.zip

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