Lab 7 - ECE 421L
Authored
by Do Le (led2@unlv.nevada.edu)
21st of October, 2020
Lab Description
The purpose of this lab is to work with buses and arrays of components.
During the lab schematics were created for the inverter, NAND gate, NOR gate, AND gate,
and OR gate. 8-bit word versions of the gates were created by using buses.
Mux/Demux were also created along with their 8-bit word versions.
Using full adders, an 8-bit adder was designed and laid out.
Prelab
Ring-Oscillator
During the pre-lab, a ring-oscillator—a circuit that generates constant pulses was made.
The ring oscillator was made using 31 inverters connected in series with a feedback loop.
Here is the resulting schematic.
![Oscillator0 Schematic](Oscillator0_Schematic.png)
Simulation of the circuit yields the following waveform.
![Oscillator0 Waveform](Oscillator0_SimulationWaveform.png)
The schematic view for the oscillator is not compact enough, but can be
replicated exactly using the following schematic.
![Oscillator1 Schematic](Oscillator1_Schematic.png)
A symbol was made for the ring oscillator.
The oscillator can be laid out by using inverter layouts created in
previous labs. To verify that the circuit matches the intended
schematic, an LVS was performed.
![Oscillator1 Layout](Oscillator1_Layout.png)
![Oscillator1 LVS](Oscillator1_LVS.png)
A simulation of the resulting cell shows that the two schematic views are equivalent.
![Oscillator1 Simulation](Oscillator1_SimulationSchematic.png)
![Oscillator1 Waveform](Oscillator1_SimulationWaveform.png)
Lab
4x Inverter:
During the first part of the lab, a 4 bit word bus inverter is designed. This is simply created by connecting
four inverters together, however, this can be done easily by using
buses and arrays as shown in the schematic below.
![Inverter4 Schematic](Inverter4_Schematic.png)
To show that this functions identically to placing down four inverter,
a transient simulation is produced using the resulting symbol.
![Inverter4 Simulation Schematic](Inverter4_SimulationSchematic.png)
Here are the results:
![Inverter4 Simulation Waveform](Inverter4_SimulationWaveform.png)
Bus NAND, NOR, AND, NOT, OR:
Using these same concepts, we can create 8-bit wide bus gates for the NAND, NOR, AND, NOT, and OR gate.
(Of course, these shortcuts do not apply to layout view).
The standard transistor level design of the one-bit input NAND, NOR, and NOT gates are shown.
The table below show the schematic design of each gate and their corresponding symbol.
Nand Transistor Level
![Nand Schematic](NAND_Schematic.png)
Nor Transistor Level
![Nor Schematic](Nor_Schematic.png)
Gates Symbols
Schematic
We can perform a simulation of the gates to verify their operation using the following schematic.
![AllGates8 Simulation Schematic](AllGates8_SimulationSchematic.png)
A transient simulation of the above yields predictable results (notice
the various delays due to the load capacitance).
![AllGates8 Simulation Waveform](AllGates8_SimulationWaveform.png)
MUX/DEMUX:
MUX and DEMUX gates are gates that allow the signal path to be
selected. In the MUX configuration, the select lines
determine which input signal is taken to the output. In the DEMUX
configuration, the select lines choose which outputs
the input connects to. Here is a schematic of a 2 to 1 MUX/DEMUX, along with it's symbol.
![MuxDemux Schematic](MuxDemux_Schematic.png)
Using this schematic view, the operation of the circuit can be verified.
![MuxDemux Simulation Schematic](MuxDemux_SimulationSchematic.png)
Here are the results of the transient simulation.
![MuxDemux Simulation Waveform](MuxDemux_SimulationWaveform.png)
Now we can create 8-bit wide word MUX/DEMUX using the concepts
introduced earlier. To keep signals compact an inverter is used
for Si within the cell. Here is the schematic followed by the new symbol.
![MuxDemux8 Schematic](MuxDemux8_Schematic.png)
![MuxDemux8 Symbol](MuxDemux8_Symbol.png)
A final verification of the 8-bit word MUX/DEMUX is performed by modifying the original schematic
used for simulation.
![MuxDemux8 Simulation Schematic](MuxDemux8_SimulationSchematic.png)
Here are the results.
![MuxDemux Simulation Waveform](MuxDemux8_SimulationWaveform.png)
Full Adder:
The final design is of an 8-bit full adder. To start, we design a single full adder that adds
inputs A, B, and Cin and generates a sum result S, and carrout result Cout. This time the whole
full adder is implemented in the transistor level and looks like this.
![FullAdder Schematic](FullAdder_Schematic.png)
A symbol is created, and simulations are ran using the symbol to verify the operations of the full adder.
![FullAdder Symbol](FullAdder_Symbol.png)
![FullAdder Simulation Schematic](FullAdder_SimulationSchematic.png)
Here are the results of the simulation.
![FullAdder Simulation Waveform](FullAdder_SimulationWaveform.png)
Lastly for the 1-bit full adder, a layout is created. To verify the
specifications are met, an LVS and DRC is done.
![FullAdder Layout](FullAdder_Layout.png)
![FullAdder DRC](FullAdder_DRC.png)
![FullAdder LVS](FullAdder_LVS.png)
Lastly, an 8-bit adder can be designed using the full adder. Using the bus and array concept, the
schematic view can be created easily, along with a corresponding symbol view.
![FullAdder8 Schematic](FullAdder8_Schematic.png)
![FullAdder8 Symbol](FullAdder8_Symbol.png)
A final verification of the design is done by adding two sets of binary numbers using this schematic.
![FullAdder8 Simulation Schematic](FullAdder8_SimulationSchematic.png)
10010110 + 01001010 = 0 11100000
![FullAdder8_SimulationWaveform_10010110_01001010](FullAdder8_SimulationWaveform_10010110_01001010.png)
10110010 + 10010011 = 1 01000101
![FullAdder8_SimulationWaveform_10110010_10010011](FullAdder8_SimulationWaveform_10110010_10010011.png)
Finally, a layout of the 8-bit adder is made by connecting 8 full
adders' carry out and carry in. Here is the layout with a DRC followed
by LVS.
![FullAdder8 Layout](FullAdder8_Layout.png)
![FullAdder8 LVS](FullAdder8_LVS.png)
With the building blocks of an ALU complete, that concludes lab 7.
The cells used in this lab can be found here at lab7_dvl.zip.
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