Lab 7 - EE421L
Authored
by Rhyan Granados
Email: granar1@unlv.nevada.edu
10/23/20
Goal
Using buses and arrays in the design of word inverters, muxes, and high-speed adders
Prelab
I backed up my work for Lab 6
![fig0.png](fig0.PNG)
I completed Tutorial 5 as seen below
Schematic:
![fig2.jpg](fig2.PNG)
Sim:
![fig1.jpg](fig1.PNG)
Sim with init. condition of osc_out at 0V:
![fig3.jpg](fig3.PNG)
Alternative More Concise Schematic:
![fig4.PNG](fig4.PNG)
Final Layout:
![fig6.png](fig6.PNG)
Schematic for Layout:
![fig8.PNG](fig8.PNG)
LVS:
![fig7.PNG](fig7.PNG)
Symbol:
![fig9.PNG](fig9.PNG)
Sim Schematid:
![fig10.PNG](fig10.PNG)
|
Sim Results:
![fig11.PNG](fig11.PNG)
|
The Lab
1) Simulate the 4-bit inverter circuit
![fig12.PNG](fig12.PNG)
![fig13.PNG](fig13.PNG)
As you can see from the
graph, since out<1> has the largest load attached to it, it will
have the longest rise time. While, out<0>takes the least amount
of time to rise due to having no load.
2) Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
Provide a few simulation examples using these gates.
|
Schematic
|
Symbol
|
8-Bit Schematic
|
NAND |
![fig15.PNG](fig15.PNG)
|
![fig14.PNG](fig14.PNG)
|
![fig16.PNG](fig16.PNG)
|
NOR
|
![fig17.PNG](fig17.PNG)
|
![fig18.PNG](fig18.PNG)
|
![fig19.PNG](fig19.PNG)
|
AND |
![fig23.PNG](fig23.PNG)
|
![fig24.PNG](fig24.PNG)
|
![fig25.PNG](fig25.PNG)
|
inverter |
|
![fig21.PNG](fig21.PNG)
|
![fig22.PNG](fig22.PNG)
|
OR
|
![fig26.PNG](fig26.PNG)
|
![fig27.PNG](fig27.PNG)
|
![fig28.PNG](fig28.PNG)
|
Simulation of all 2-input gates:
![fig30.PNG](fig30.PNG)
![fig29.png](fig29.png)
3)
Next examine the following schematic of a 2-to-1 DEMUX/MUX (and the
symbol). Simulate the operation of this circuit using Spectre and
explain how it works.
1-Bit Mux/Demux
Schematic
![fig31.PNG](fig31.PNG)
|
![fig32.PNG](fig32.PNG)
|
1-Bit 2:1 Demux/Mux
Schematic
![fig33.PNG](fig33.PNG)
|
![fig34.PNG](fig34.PNG)
|
1-Bit 2:1 Mux Sim
![fig36.PNG](fig36.PNG)
![fig35.PNG](fig35.PNG)
As we can see on the
simulation, the multiplexer works by using S to choose the output
signal Z. So if S is high then it will pass A's signal as the output Z,
and if S is low(Si becomes high due to the inversion) and B's signal is
passed through as the output Z.
1-Bit 2:1 Demux Sim
![fig37.PNG](fig37.PNG)
![fig38.PNG](fig38.PNG)
As we can see from the sims
the demultiplexer does the opposite of the multiplexer. Instead of
using S to choose which signal to pass through as the output Z, it
takes Z as the input and uses S to decide where Z will go. So if S is
high then Z goes to A and inversely goes to B when it's low.
4) Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.Include
an inverter in your design so the cell only needs one select input, S
(the complement, Si, is generated using an inverter).Use simulations to verify the operation of your design.
Note: So I already included the inverter in part 3) so I will just re-use it
8-Bit 2:1 Mux Sim
![fig39.PNG](fig39.PNG)
![fig40.PNG](fig40.PNG)
8-Bit 2:1 Demux Sim
![fig41.PNG](fig41.PNG)
![fig42.PNG](fig42.PNG)
5) Simulate the operation of your 8-bit adder.
1-Bit Full Adder
Schematic
![fig43.PNG](fig43.PNG)
|
![fig44.PNG](fig44.PNG)
|
8-Bit Full Adder
Schematic
![fig45.PNG](fig45.PNG)
|
![fig46.PNG](fig46.PNG)
|
Simulation
![fig47.PNG](fig47.PNG)
Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
Show that your layout DRCs and LVSs correctly.
Layout
![fig48.PNG](fig48.PNG)
DRC and LVS Certification:
![fig49.PNG](fig49.PNG)
![fig50.PNG](fig50.PNG)
File Back-up Proof
![51.PNG](51.PNG)
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