Lab

Lab 6 - EE421L

Authored by Rhyan Granados

10/15/20

Goal

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder

Prelab

I carefully followed Tutorial 4 in which we are taught how to design a schematic, symbol, and layout of a 6u(width) by 0.6u(length) nand gate. We also ran a simulation with our nand gate in a circuit.

Nand Symbol	Nand Schem
Nand Layout	Nand in a Circuit

DRC Certification	LVS Certification
Simulation Results

The Lab

1) Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)

2-input NAND gate (Fig. 12.1) (since this was the same as the nand gate we made in tutorial 4, I will re-use it but with my initials(R.G. NAND) in the middle of the symbol this time and the cell names renamed to (NAND_RG_f20).

2-input Nand Symbol	2-input Nand Schem
2-input Nand Layout	2-input Nand in a Circuit

As you may have noticed on my Tutorial 4 LVS certification, the LVS netlists matched but the parameters for the schematic (W=6u) and layout(W=12u!!) were off. Tutorial 4 didn't show to fix it, but I will explain how to now. This problem is caused by copying and pasting the inverter layout, so to remedy this, we need to edit the parameters of the PMOS and change the width to 6u.