Lab 7 - EE 421L 

Author: Edgar Amalyan
Email:  amalyane@unlv.nevada.edu
Date:   11/04/2020

Goals:
In this lab, we will design, layout, and simulate a ring oscillator, various logic gates, a multiplexer/demultiplexer, and a full-adder.
They will be constructed from 1-bit versions which will be used to build 8-bit array versions.
These components can then be used to build an ALU.

Prelab  

Note: Everything is a different aspect ratio, so I just made them all relatively square so the page can be less of an eye-sore. Please click on pictures for larger and less funky views.

Tutorial 5

Schematic

prelab/sch.png

Simulation (using Symbol)

prelab/sim_sch.png prelab/plot.png

Layout and DRC

prelab/layout.png     prelab/drc.png

Extraction and LVS

prelab/extracted.png     prelab/lvs.png



Lab

4-bit Inverter

lab/4_BIT_INVERTER/sch.png


lab/4_BIT_INVERTER/sim_sch.png    lab/4_BIT_INVERTER/plot.png

The capacitors smooth the output. The larger the capacitor, the more energy it has to be used when needed. But it also means more time to charge and discharge, increasing the rise/fall times.

8-bit Array Inverter

lab/8_BIT_INVERTER/sch.png

lab/8_BIT_INVERTER/sch_HL.png

For the simulations, we can plot all 8 elements of the array to make sure the connections are correct.

lab/8_BIT_INVERTER/sch_simL.png    lab/8_BIT_INVERTER/plot.png

8-bit Array NAND

lab/8_BIT_NAND/sch.png

lab/8_BIT_NAND/sch_HL.png

lab/8_BIT_NAND/sch_sim.png    lab/8_BIT_NAND/plot.png


8-bit Array NOR

lab/8_BIT_NOR/sch.png

lab/8_BIT_NOR/sch_HL.png

lab/8_BIT_NOR/sch_sim.png    lab/8_BIT_NOR/plot.png


8-bit Array AND

lab/8_BIT_AND/sch.png

lab/8_BIT_AND/sch_HL.png

lab/8_BIT_AND/sch_sim.png    lab/8_BIT_AND/plot.png


8-bit Array OR

lab/8_BIT_OR/sch.png

lab/8_BIT_OR/sch_HL.png

lab/8_BIT_OR/sch_sim.png    lab/8_BIT_OR/plot.png


2-to-1 MUX

lab/MUX_DEMUX/sch.png

We can simulate both the MUX and DEMUX together by just reversing their inputs/outputs.

As can be seen below:
S  = 1 => Out = A
Si = 1 => Out = B

and of course the reverse for the DEMUX.

lab/MUX_DEMUX/sch_sim.png    lab/MUX_DEMUX/plot.png


2-to-1 8-bit MUX

lab/8_BIT_MUX_DEMUX/sch.png


We can note that the middle logic levels are due to transistions occuring at the same time. The timings must be set appropriately.

As seen below:
S  = 1 => Out = A
Si = 0 => Out = B


lab/8_BIT_MUX_DEMUX/sch_sim.png    lab/8_BIT_MUX_DEMUX/plot.png


1-bit Full-Adder

lab/1_BIT_FA/sch.png

lab/1_BIT_FA/sym.png

lab/1_BIT_FA/layout.png    lab/1_BIT_FA/drc.png

lab/1_BIT_FA/extracted.png    lab/1_BIT_FA/LVS.png

8-bit Array Full-Adder

lab/8_BIT_FA/sch.png

lab/8_BIT_FA/layout.png    lab/8_BIT_FA/drc.png

lab/8_BIT_FA/extracted.png    lab/8_BIT_FA/LVS.png

To verify the operation of my 8-bit Array FA, I added two numbers. In simulation paramters, I had A = 10111001
(185) + B = 01000101 (69) = 11111110 (254)

lab/8_BIT_FA/sch_sim.png    lab/8_BIT_FA/plot.png



Backups:

As demonstrated in Lab 1, I run ./backup.sh from the Cadence server and download the 'Backup' folder containing the compressed archives of my CMOSedu and entire home directories.
All files pertaining to this lab report already exist and are directly edited from another folder that also gets synced.
I run sync_to_gcp.bat from my computer which makes my GCP Storage bucket identical to my local directory.

backup_cadence

backup-labs

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