Lab 5 - EE 421L 

Author: Edgar Amalyan
Email:  amalyane@unlv.nevada.edu
Date:   10/07/2020
Goals:
This lab focuses on the layout and simulations (IV curves) of NMOS and PMOS transistors.
Prelab  

Note: Click on pictures for larger views.

Tutorial 3
Here we go through the creation of a CMOS Inverter (NOT Gate).

First we draw the schematic for the inverter. An inverter consists of an PMOS connected in series with a PMOS. When the input is 0, the output is 1, and when the input is 1, the output is 0.

tutorial3_sch.png

Now we can create a symbol for the our inverter from the schematic.

tutorial3_symb.png

We can go ahead and simulate the inverter to verify its operation.

tutorial3_sim.png

Now we can move on to the layout. As mentioned, the inverter is a PMOS in series with a NMOS. We need to implement this in our layout by making the appropriate terminal connections.

tutorial3_layout.pngtutorial3_layout.png

At this stage we should DRC our layout.

tutorial3_drc.pngtutorial3_drc.png

We extract the view to run the LVS.

tutorial3_extracted.png

We run the LVS.

tutorial3_lvs.png

We can now simulate the extracted view.

tutorial3_sim_extracted.png

Lab

The lab is similar to the prelab.

Inverter - 12u/6u

First we will create a 12u/6u inverter.

We start with the schematic.

12u_6u_sch.png

We create a symbol.

12u_6u_symb.png

We start the layout.

12u_6u_layout.png

We DRC.

12u_6u_drc.png

Extract.

12u_6u_extracted.png

LVS.

12u_6u_lvs.png

Create a schematic to simulate the inverter we just layed out.

12u_6u_sim_sch.png

The operation of a NOT gate is obvious, 0 in 1 out or 1 in 0 out. To demonstrate the actual differences between how an inverter is physically designed, we can add a capacitor at the output. The effects will soon become clear.

We can vary the value of the capacitor from 100fF to 100pF in 10x steps. Instead of simulating 4 different times, we can just run a parametric analysis.

12u_6u_parametric_spectre.png

12u_6u_spectre.png

All simulations thus far have been done using the Spectre tool in Cadence. There are other simulation programs available, one of them being UltraSim. Ultrasim can give us quicker results (for Transient Analysis) with less accuracy. Let's try it out.

Note: Make sure you to save states and the parametric analysis to avoid having to redo it everytime. If there are errors, make sure to check the simulator being used and that the model files are loaded.

12u_6u_parametric_ultrasim.png

12u_6u_ultrasim.png

The top waveform is the input. Digitally, it goes from 0 to 1 and then back down to 0. We expect the output to be inverted, that is, to go from 1 to 0 and then back up to 1.
When the capacitor has a small value, this is almost the case (notice it is not perfect). As the capacitance increases, so does the delay. When the time constant is large enough, there is almost no change in the output as the capacitor has sufficient charge to keep the output where it was originally.


Inverter - 48u/24u

Now let's design a 48u/24u inverter. We repeat the above process with the relative adjustments.
Schematic.

48u_24u_sch.png

Symbol.

48u_24u_symb.png

Layout.

48u_24u_layout.png

DRC.

48u_24u_drc.png

Extract.

48u_24u_extracted.png

LVS.

48u_24u_lvs.png

Simulation Schematic.

48u_24u_sim_sch.png

Spectre:

48u_24u_parametric_spectre.png

48u_24u_spectre.png

UltraSim:

48u_24u_parametric_ultrasim.png

48u_24u_ultrasim.png

The 4 finger inverter has more area, allowing more current to flow through to the capacitor. It seems that the delay was not solely due to the time constant of the capacitor, but also the surrounding circuitry.
In the past we have always simulated and characterized curcuits using ideal components. Now we can clearly see the limitations of real world devices.

The design files used for this lab are provided here: lab5_ea.zip

Backups:

As demonstrated in Lab 1, I run ./backup.sh from the Cadence server and download the 'Backup' folder containing the compressed archives of my CMOSedu and entire home directories.
All files pertaining to this lab report already exist and are directly edited from another folder that also gets synced.
I run sync_to_gcp.bat from my computer which makes my GCP Storage bucket identical to my local directory.

backup_cadence

backup-labs

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