Lab 6 - EE 421L 

Authored by Biruk Gebremeskel

Email: gebreb1@unlv.nevada.edu

October 24, 2018

Lab description:

The purpose  of this lab was to design, layout, and simulate CMOS NAND and XOR gates and a Full Adder.

Pre-Lab Work:

All previous labs have been backed up in Dropbox.

Finished Tutorial 4

Lab Work

Exercise-1:

Design, layout,DRC, extract, and LVS a 2-input NAND gate

2-input NAND gate Schematic	2-input  NAND gate Symbol
2-input NAND gate layout	2-input  NAND gate Extracted
2-input  NAND gate DRC	2-input  NAND gate LVS

Exercise-2:

Design, layout,DRC, extract, and LVS a 2-input XOR gate

2- input XOR Schematic	2-input XOR Symbol
2-input XOR layout	2-input XOR Extracted
2-input XOR DRC	2-input XOR LVS

Exercise -3:

Simulations of NAND gate, XOR gate, and Inverter

NAND gate, XOR gate, and Inverter Schematic

NAND gate, XOR gate, and Inverter Simulation

Truth Table for NAND gate and XOR gate

Full Adder Layout

Full Adder Extracted

Full Adder DRC

Full Adder LVS

Full Adder Truth Table