Lab 6 - ECE 421L
Authored by Brett Smith (smithb25@unlv.nevada.edu)
Tuesday, October 24th, 2017
The first step of this lab was to design 2-input NAND and XOR gates to complement the inverter I designed in a previous lab. The NAND is not exactly rocket science, but I was pretty happy with my XOR layout.
 NAND2 symbol |
 XOR symbol |
 NAND2 layout |
 XOR layout |
 
NAND2 DRC and LVS |
 
XOR DRC and LVS |
As you can see below the gates act more or less as expected. Unsurprisingly the NAND2 and XOR gates don't handle the gate inputs changing simultaneously. The gates I drafted seem to have a propagation delay on the order of 2ns. This means that for around 2ns after a gate's input changes the output is unreliable because it is susceptible to glitches. The simplicity of the inverter prevents it from having the same issues.
 gate simulation schematic |
 gat simulation results |
With all of the component parts already created I moved on to designing a full adder device. I drafted the gated to use standard cells of the same height so that I could place them all next to each other in the layout. I had to use metal2 for the full adder, but I was able to adhere to metal1 running vertically and metal2 running horizontally in order to minimize cross contamination and noise.
 Full adder symbol |
 Full adder symbol |
 Full adder layout |
|
 Full adder extracted layout |
|
 Full adder DRC |
Full adder LVS |
I simulated my full adder design. It performed as desired with a similar propagation delay to it's component gates. In application I would probably use a delay of 5ns to completely eliminate issues with glitches. As you can see the schematic and extracted models simulate with nearly identical behaviour.
 Full adder schematic |
 Full adder results |
 Full adder extracted results |
THe library for my design can be downloaded here. Both my lab and this website have been backed up.