Lab 4 - EE 421L 

Authored by Trevor Ensign

ensigt1@unlv.nevada.edu

September 27, 2017 
  

Pre-Lab Work

For the prelab, Tutorial 2 was completed. This involved learning how to simulate and layout PMOS and NMOS devices. 

Lab Work

For the first part of this lab, we performed 4 different current vs. voltage analysis for PMOS and NMOS devices. The test are listed below. 

• ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. 6u/600n width-to-length ratio.
• ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.  6u/600n width-to-length ratio. 
• ID v. VSD  of a PMOS device for VSG  varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. 12u/600n width-to-length ratio. 
• ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. 12u/600n width-to-length ratio.  

You can download files for this lab here.

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