Lab 3 - ECE 421L 

Authored by John Dye (dyej1@unlv.nevada.edu),

September 20th, 2017

  

Lab description:

In this lab, we will take the Schematic developed in Lab 2 and convert it into a Layout, then go through verification processes to ensure that the Layout is formatted correctly in matching the Schematic

Prelab:

All of my previous work has been backed up on Google Drive.

Lab Report:

To start out with, the dimensions of the n-well resistor need to be known.
To do this, start with,
R_total = 10k = R_square * W/L = (800) W/L
To match the dimensions of the n-tap, let L=3.6
10k=800 W/(3.6)
W = 45

With that information, the layout can now be built.
      To make the resistors match the lengths given above, it is a good idea to start by laying out a rectance, then selecting the rectangle and pressing "Q". Once the menu pops up, simply input the desired dimensions.
      Doing this several times to create one group of resistors, then copying all of the resistors results in the following total and zoomed in layouts,
Total Layout      Zoomed in Layour
In the right picture, you can see the initial configuration as well as the second set of resistors. The layout of the bottom three resistors were then copied down to the rest of the 8 sets of resistors in order to create the overall schematic. When copying, the settings were set to "orthogonal" to ensure that all of the resistors are at the same x value, but differing y values.
 
      When DRC'd, the dialogue window displayed,
Textbox

Meaning there were no technical errors within the Layout.
      In the extracted view, the values of the resistors resulted out to be,
Resistor Value
Which is acceptably close to R=10k.

      The main issue I ran into with this lab was attempting to run the LVS. Everytime I tried to LVS, the following error box came up,
Error
So I was unable to successfully run the LVS. I will discuss this issue with Dr. Baker during this week's lab and hopefully have it solved before next lab report.

        This lab and its associated materials have been backed up in google drive, and the schematic and layout files have been zipped up and attached within the lab report folder.

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