Lab Project - EE 421L
The Inverter:
| Schematic | Schematic Simulation |
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| Layout | Waveform |
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| Extracted | LVS |
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The Xor:
| Schematic | Schematic Simulation |
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| Layout | Waveform |
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| Extracted | LVS |
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The Buffer:
| Schematic | Symbol |
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| Layout | Extracted |
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The Even Parity Checker:
- The inputs to my circuit are D0-D7, P and the output is check
- The output of the design, check, is buffered before connecting to a pad
- The parity input is "xor'd" to the even binary set of inputs to determine if the output is TRUE
- An even binary set of inputs include D0-D7 and the parity input
| Schematic | Symbol |
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| Layout | Extracted |
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| LVS | DRC |
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| Schematic Simulation | Waveform |
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| Extracted Simulation | Netlist Display |
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