Lab 6 - ECE 421L
Authored by Staford Snow, snows4@unlv.nevada.edu
10/26/2016
Lab description: In this lab, I drafted schematics, created
symbols, designed layouts, and simulated a 2-input NAND and XOR gate using
6u/0.6u MOSFETs. Following the
completion of the gates, I drafted a schematic, created a symbol, designed a
layout, and simulated a full adder circuit using my gates.
Pre Lab: Following the lab instruction, I backed up
all of my work from the lab and course.
I next followed the procedure described in Tutorial
4.
Lab:
To begin the
lab, I drafted the schematics for the 2-input NAND and XOR gates. The gates utilized 6u/0.6u MOSFETS.

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