Lab 3 - ECE 421L 

Authored by Isaac Robinson,

robins82@unlv.nevada.edu

September 21st, 2016

  

This lab focuses on the layout of the 10-bit DAC designed and simulated in Lab 2.

The MOSIS scalable CMOS design rules implements a lambda of 300nm.
The mimimum width of n-well is 12 lambda:
300nm * 12 = 3.6 microns

Using this information we choose 4.5um as our width.

To determine our length:
R = (L * R[]) / W
thus
L = (R * W) / R[] = (10k * 4.5um) / (800) = 56.25um

But to allign the resistor to grid the value needs to be divisible by 0.15 microns.
4.5 / 0.15 = 30
56.25 / 0.15 = 375
(Note the tutorial used 56.1 [56.1 / 0.15 = 374] instead of 56.25 so this value is used in the lab)

Image: The n-well resistor
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Image: The calculated value of resistance for the n-well resistor.
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The width and length jof the resistor can be measured using the ruler tool in layout mode.
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CLICK HERE for my final design directory.
 
 
 
 

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