Lab 8 - EE 421L 

Authored by:

Dominique Anguiano - anguian3@unlv.nevada.edu

Michael Ghisilieri - ghisilie@unlv.nevada.edu

Martin Jaime - jaimem5@unlv.nevada.edu

Billy Louis - louisb2@unlv.nevada.edu

October 26, 2016

  

Lab chip for this project:  Chip6_f16

 

Chip Devices

The chip contains the following devices

    - A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load

    - NAND and NOR gates using 6/0.6 NMOSs and PMOSs

    - An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS

    - 20k resistors, one made using n-well and the other using hi-res poly2

    - 12u/0.6u PMOS and NMOS devices

 

Schematic, DRC, and LVS of each device

 

A 31-stage ring oscillator (top) with a buffer (bottom) for driving a 20pF off-chip load

 

ring_osc_schematic.jpegring_osc_DRC.jpegbuffer_LVS.jpeg
buffer_schematic.jpegbuffer_DRC.jpegbuffer_LVS.jpeg

 

NAND (top) and NOR (bottom) gates using 6/0.6 NMOSs and PMOSs

 

nand2_schematic.PNG
nand2_DRC.PNG
nand2_LVS.PNG
nor2_sch.PNGnor2_drc.PNGnor2_lvs.PNG

 

 

An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS

 

Inverter_Schematic.PNGInverter_DRC.PNGInverter_LVS.PNG

 

 

20k resistors, one made using n-well (top) and the other using hi-res poly2 (bottom)

 

20k_n_well_schematic.PNG20k_n_well_DRC.PNG20k_n_well_LVS.PNG
20k_poly2_schematic.PNG20k_poly2_DRC.PNG20k_poly2_LVS.PNG

 

 

12u/0.6u PMOS (top) and NMOS (bottom) devices

 

pmos_12u_sch.PNGpmos_12u_drc.PNGpmos_12u_lvs.PNG
nmos_12u_sch.PNGnmos_12u_drc.PNGnmos_12u_lvs.PNG

 

 

Schematic and layout of padframe

  

SonOfMonster.PNGMonster.PNG
 

 

Pin Chart

 

pin_chart.png  

  

 

 

 

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