Lab 6 - ECE 421L
The files used in this lab can be found here.
Pre Lab
Once again, the prelab for this week had us layout a device that would be used in the lab for this week. The device created this time was a two-input NAND gate. The prelab covered the creation and layout of this device and had us run the usual LVS and DRC checks for the NMOS device. This was the only task the pre lab had us do, besides backing up all of our files of course.
Lab Report
1) Draft the Schematics of a 2-input NAND gate and a 2-input XOR gate using 6u/.6u MOSFETS
The 2-input NAND gate
Since the pre-lab for this week already had us work on the NAND gate, we will begin there first. The schematic, symbol, layout, and extracted view for the NAND gate can be seen below.
Also, the DRC and LVS for the NAND2 gate can be seen in the layout and extracted screenshots respectively.
The 2-input XOR gate
The Schematic, Symbol, Layout and Extracted view of the 2-input XOR gate can be seen below.
And of course, we also have the DRC and LVS results for the above layout.
Spectre Simulations for the logical operations of the gates
Simulation of all three of the gates was done at the same time in order to be able to observe their output on a graph at the same time.
The schematic and results of the simulation can be seen below. The Inverter is on the top, NAND in the middle and XOR on the bottom.
The results of the simulation can be seen in the table below.
As can be seen from the simulation, each of the gates appears to be functioning properly. However there does appear to be a point in the graph at 200ns where the output appears to glitch out. This appears to be caused by the simultaneous switching of levels of both of the inputs to the gates. This glitch only appears for a very short time though and vanishes once the input levels finish their transitions. The presence of this glitch does not appear have any lasting effects to the output.
Setting up vpulse
Setting up the voltage source is a crucial part of testing the function of these gates. In order to effectively test them, the levels of both gate inputs must alternate between 00, 01, 10, and 11, for the 'a' and 'b' input respectively. This can easily be done by having a delay on the voltage sources and having them alternate between on and off after a certain time period. The setup of V0 can be seen below. The setup of V0, was used for the voltage source V0 in the above schematic and results in the waveform of 'A' that can be seen above. V2, changes the delay time, pulse width and period to be half of that of V0 in order to obtain the waveform seen for 'B' in the simulation above.
2) Creation of a Full Adder
Using the XOR and NAND gates that were created above, it is possible to create a full-adder which adds two one-bit values together. The schematic for the full-adder using the gates created in this lab can be seen below. The symbol for the full-adder may also be seen below.
In order to ensure that the full adder works properly, a simulation was ran using the symbol in the schematic seen below.
The output results of the full-adder may be seen in the table below.
As we can see, the full adder is able to properly add the two one-bit values and the carry in bit to generate its own sum and carry out bit. The glitches that were seen in the above simulations of the gates can also be seen here and happen at the points where both 'a' and 'b' are changing values simultaneously.
Layout of the full-adder
