Project: Digital Design Lab Final Project - EE 421L     

Email: yurgelon@unlv.nevada.edu

October 21st, 2015

Project Description:

First half of the project (no layout, just schematics and symbols), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 9. 

Ensure that you have schematics with simulations for all of the cells listed below.

Your up/down counter, for example, should be simulated showing, counting up, down, or both, resetting then counting, etc.

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.  

Dr. Baker will go over your designs with you, including running simulations, when lab meets on Nov. 9.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 23.

Again, I will meet with you on Nov. 23 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

Finishing the projects by Nov. 23 will give us time to assemble chips for fabrication through MOSIS. 

• Design of an 8-bit resettable (input "clear") up/down counter 
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   

•   ALL OF THE DESIGN FILES ASSOCIATED WITH THIS LAB CAN BE FOUND HERE.                                  

• The 8-bit counter below has a few inputs that are not detailed in the specifications. The below counter also contains a synchronous load, flip-flop asynchronous set, and enable line while maintaining the clear option listed above. As one can see below, the overall 8-bit counter has been bit sliced to clean up schematics, and make the presentation cleaner. The single bit schematic shown in Fig. 1 consists of two XOR gates, one AND gate, a 2-1 MUX/DEMUX, and a D-FF. The operation of the input/outputs is listed in the table below. 

Fig. 1 - 1-bit Version of the Counter	Fig. 2 - 8-bit Version of the Counter
Fig. 3 - Counter Starting at 0 and Counting Up	Fig. 4 - Counter Starting at 256 and Counting Down
Fig. 5 - Counter Starting from 0, Counting Up to 12 and then to 0	Fig. 6 - Counter Counting Up; Clear is Asserted, and Register Contents Cleared
Fig. 7 - Counter Counting Up from 256, Load sets contents to 256, and then Clear Resets the Registers	Fig. 8 - Counter Begins Counting Down From 256, then 256 Gets Loaded in, Counts Down/Up till Overflow
Fig. 9 - Counter DRC Clean	Fig. 10 - Counter LVS Clean
Fig. 11 - Counter Layout
Fig. 12 - Buffer Schematic	Fig. 13 - 8-bit Counter with Buffered Outputs
Fig. 14 - Buffered Output Counter DRC Clean	Fig. 15 - Buffered Output Counter LVS Clean
Fig. 16 - Buffered Output Counter Layout

• Below one can see the operation of all of the necesarry gates, and flip-flops needed to create the counter above.  

Fig. 17 -  D- FF with Asynchronous Clr and Set	Fig. 18 - D - FF Operation Simulation
Fig. 19 - Test of Logic Gates; NAND Gates: AND Gates	Fig. 20 - Simulation of Logic Gates
Fig . 21 - Test of Logic Gates; XOR Gate	Fig. 22 - Smulation of Logic Gates
Fig. 23 - NAND DRC Clean	Fig. 24 - NAND LVS Clean
Fig. 25 - XOR DRC Clean	Fig. 26 - XOR LVS Clean
Fig. 27 - 2/1 MUX/DEMUX DRC Clean	Fig. 28 - 2/1 MUX/DEMUX LVS Clean
Fig. 29 - D-FF  DRC Clean	Fig. 30 - D-FF LVS Clean

    Exercise #2: A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load

• Due to the output of the ring oscillator needing to drive a 20 pF off-chip load, a buffer needed to be created to do so. During my testing, I found that by using an A multiplier of x8, a stage of m = 64 was enough to drive the load decently. More stages would make the edges of the resulting waveform sharper, but would take up significant space on the chip. This trade-off becomes a key point, and as such, I decided that the m = 64 stage was enough.

Fig. 31 - Simulation of the Inverter Used in the Oscillator	Fig. 32 - Output of the Inverter Logic Gate
Fig. 33 - 31 Stage Ring Oscillator Schematic	Fig. 34 - 31 Stage Ring Oscillator Simulation with No Load
Fig. 35 - 31 Stage Ring Oscillator with 20 pF Buffer	Fig. 36 - 31 Stage Ring Oscillator with Buffer Simulation with 20 pF Load
Fig. 37 - 31 Stage Oscillator DRC Clean	Fig. 38 - 31 Stage Oscillator LVS Clean
Fig. 39 - 20 pF Buffer DRC Clean	Fig. 40 - 20 pF Buffer LVS Clean
Fig. 41 - OSC with Buffer DRC Clean	Fig. 42 - OSC with Buffer LVS Clean

• I was able to create the schematics for each of the following gates, and then simulate them to verify their operation. 

Fig. 43 - NAND Simulation Schematic	Fig. 44 - NAND Simulation
Fig. 45 - NOR Simulation Schematic	Fig. 46 - NOR Simulation
Fig. 47 - NAND Internal Schematic	Fig. 48 - NOR Internal Schematic
Fig. 49 - NOR Gate DRC Clean	Fig. 50 - NOR Gate LVS Clean
Fig. 51 - NAND Gate DRC Clean	Fig. 52 - NAND Gate LVS Clean

 Exercise #4: An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS

• Below are the two sizes of inverters. Their operation is verified by the simulation on the right hand side. 

Fig. 53 - 12u/6u Inverter Simulation Schematic	Fig. 54 - 12u/6u Inverter Simulation
Fig. 55 - 6u/6u Inverter Simulation Schematic	Fig. 56 - 6u/6u Inverter Simulation Schematic
Fig. 57 - 6u/6u Inverter DRC Clean	Fig. 58 - 6u/6u Inverter LVS Clean
Fig. 59 - 12u/6u Inverter DRC Clean	Fig. 60 - 12u/6u Inverter LVS Clean

 Exercise #5: Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)

• Below is the schematic and symbol for each transistor. They have be simulated by showing their characteristic curves. 

Fig. 54 - NMOS Schematic	Fig. 55 - NMOS Symbol
Fig. 61 - PMOS Schematic	Fig. 62 - PMOS Symbol
Fig. 63 - NMOS VDS Sweep
Fig. 64 - NMOS VGS Sweep
Fig. 65 - PMOS VSD Sweep
Fig. 66 - PMOS VSG Sweep
Fig. 67 - NMOS DRC Clean	Fig. 68 - NMOS LVS Clean
Fig. 69 - PMOS DRC Clean	Fig. 70 - PMOS LVS Clean

• The simulation below shows that the schematic is functioning properly. One can also see that the 25k N-Well resistor is available for use. 

Fig. 71 - Resistor Divider Schematic	Fig. 72 - Resistor Divider Simulation Schematic
Fig. 73 - Resistor Divider Simulation Results
Fig. 74 - 25k Resistor/Divider DRC Clean	Fig. 75 - 25k Resistor/Divider LVS Clean
Fig. 76 - 25k Resistor DRC Clean	Fig. 77 - 25k Resistor LVS Clean

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