Lab 2 - ECE 421L 

Authored by Dillon Hageman 

hageman2@unlv.nevada.edu

09/13/15

Overview: In this lab we used cadence to design a 10 bit DAC from scratch and used our designed DAC along with an ADC to simulate the circuit and see how it would react to different circumstances such as driving a load.

Prelab: In the prelab we simulated the ideal ADC and DAC design shown below

Running a 1 microsecond transient analysis of this schematic gave us, as expected, the following output graph.

Our input was a 5 volt sine wave, and our output was a very similar waveform with a small step voltage. This step voltage can easily be calculated by putting Vin/2^(n) where n is the number of bits. Because our input voltage was 5 volts and it is a 10 bit converter, the calculation of the step voltage is 5/2^10=4.88mV
Now that was know how the ideal ADC to DAC input/output graph look, we can begin our design of our own DAC for use in the schematic.

We want to test the time delay of the circuit with a 5 volt pulse connected to b9 and the rest of the inputs grounded and a 10pF capacitor connected to the output as shown

Our expected value can be found with a simple calculation using 0.7RC=0.7(10k)(10p)=70 nS. The graph below shows that our hand calculations were correct and we get a value of about 70nS for the delay. Our output is halfed because we are using 2^9 instead of all 2^10 bits, which is half of the bits. This is shown in the output graph below

Lab 2 process and explanation


The above picture shows the first step of our design of our DAC, which involves creating the basic schematic of the 2R resistor and the R resistor, with the value of R here being 10k. To simplify the schematic, we turn this basic circuit into a symbol by creating a cell view from the schematic's cell view which results in the following

This shows the symbol view for the Rdiv circuit shown above with the three pins. This symbol represents one bit of our DAC, so we combine ten of these into a schematic four our desired schematic of a 10 bit DAC as shown below

As done previously, We then take this final schematic our our DAC and turn it into a symbol view to simplify the design by taking the cell view of this design to create the symbol. Doing so results in the following

Now that we have our 10bit DAC, we want to replace the ideal one used in our prelab simulation with ours and run the same transient analysis as in the prelab to check the results. The result of which is shown below. The circuit shows the schematic for our final simulation in which we tested it with both a resistor and capacitor in parallel to ground. The first simulation is just done without either of these components, the second is done with just the resistor connected, the third was done with just the capacitor connected, and the final sim was done with both connected as shown below.



This graph of our Vout is very similar to our original simulation as it was expected to be. The step voltage shows that the conversion is still taking place. The next step is to test the design's response to added components.  First, we will add a resistor with a value the same as our R value, 10k. The expected result would be a the 5 volt input being split in half to a 2.5 volt output, as the resistance of our 10bit DAC should be R(10k). This graph is shown below

As expected, our output graph peaks at 2.5 volts when the input is at 5 volts. This shows that our DAC was designed correctly and does in fact have a resistance of R(10k) as it should. The reason that the resistance of the 10 bit converter should be 10k is shown in the lab explanation

While the above circuit is just a 5 bit converter, it still demonstrates the same process that is occuring and why the resistance obtained should be R. Starting from the top, the b4 2R and the b3 2R are in parallel and therefore the equivalent resistance is just R. Then that Req is in series with R and once again becomes 2R. This continues on through all of the bits until the final bit of the process, in which we are eventually left with two 2R resistors in parallel which will give us our final result desired as a resistance of R, which in our case is 10k. So when a 10k load is added between the output of our DAC and ground, it acts as a voltage divider between two equivalent resistances which is why we ended up with our output waveform having half the voltage of our input.

Next, by adding a capacitor in place of where the resistor was, we would expect the capacitor to smooth out the square looking steps into a more sine wave looking curve. The result of our simulation with a capacitor connected between Vout and ground is shown below.

As expected, the capacitor did smooth out the waveform. What I didn't expect at the time was the slight drop in output voltage in doing so. When I thought about it, it made sense however and the reason Vout is slightly less than Vin is due to the fact that the capacitor is not ideal and has built in impedance.

Next we look at what happens when both of these processes are combined and we use a resistor to limit the output voltage and use a capacitor to smoothen out the curve. This simulation resulted in the following

As we hoped the simulation showed that the two combined to both limit the output of the converter as well as smoothen out the curve.

In a real circuit the switches are implemented with mosfets. This means that our converter is no longer ideal and that our switches actually will have a built in resistance. If this resistance is not small compared to R, this will actually hugely effect our output. For example, if the switches in this design had a resistance of 1ohm, our Vout would be about 99.9% of our Vin voltage and the built in resistance of the mosfets would be very negligible. However, if the built in resistance was much larger than that it would become a huge hinderance to the performance and for example a built in resistance of 1k would result in about a 90% output and this would scale up quickly. So for practical design I think it's safe to assume that large resistors are better for accuracy when we want to neglect the mosfet resistances.

I once again backed up my lab files into my google drive

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