Lab 5 - ECE 421L 

Authored by Michael Villalba 1008445138,

10/13/2014

  

Design, layout, and simulation of a CMOS inverter

In this lab we will design an inverter using the NMOS and PMOS used in previous labs. Firs thing to do is go through Tutorial_3 to get familiar with the lab.


First thing we did was design a schematic for a 12u/6u inverter making sure the multiplier is 1. (PMOS/NMOS width)

12:6_schematic.png

There are two pins connected to the schematic, A for the input and Ai for the inverted output. Next thing to do is create a symbol for the 12u/6u inverter.

12:6_sym.png

After creating the symbol we now need to create a layout for the 12u/6u schematic.

12:6_layout.png

After creating the layout we need to DRC to make sure it passes and that there are no errors. Once it passes we can now extract the layout.

12:6_extracted.png

Now that we have our extraction LVS our schematic with the extraction to make sure they match.

12:6_LVS.png

We get the notification that the LVS is a match but we still want to check the output of the LVS just for a double confirmation.

12:6_LVS_output.png

Now we will repeat the previous steps making a 48u/24u inverter with a multiplier of 4.

48:24_schem.png

48u/24u symbol:

48:24_sym.png

Layout:

48:24_layout.png

Extraction:

48:24_extract.png

LVS net-list match:
48:24_LVS.png
48:24_LVS_Out.png

Will now simulate the inverters while changing the capacitors with a 100f, 1p, 10p, 100p then compare. We are going to use Spectre then use UltraSim which is just a faster way to simulate when using trans in Cadence.
This is the first run of simulations using the 12u/6u inverter.

sim_12:6.png

100fF:

Spectre                                                                            UltraSim

12:6_100f_spec.png12:6_100f_ult.png


1pF:

Spectre                                                                              UltraSim

12:6_1p_spec.png12:6_1p_ult.png

10pF:

Spectre                                                                            UltraSim

12:6_10p_spec.png12:6_10p_ult.png


100pF:

Spectre                                                                                UltraSim

12:6_100p_spec.png12:6_100p_ult.png


Now we will run the same simulations for the 48u/24u inverter.


sim_48:24.png


100fF:

Spectre                                                                                        UltraSim

48:24_100f_spec.png48:24_100f_ult.png



1pF:

Spectre                                                                                                             UltraSim

48:24_1p_spec.png48:24_1p_ult.png



10pF:

Spectre                                                                                                            UltraSim

48:24_10p_spec.png48:24_10p_ult.png



100pF:

Spectre                                                                                                            UltraSim

48:24_100p_spec.png48:24_100p_ult.png


From the simulations we see that the smaller the capacitance load, the faster the charge and discharge. The difference between the 12u/6u inverter and the 48u/24u inverter is that the 48u/24u inverter seems to charge and discharge faster due to the increased width that allows more current passing. There wasn't too much of a difference with the UltraSim, just wasn't as accurate but still good enough to use for future simulations.

This concludes lab 5!


Michael's Lab 5 files can be downloaded here.


Here is me backing up my work to dropbox.

zip_backup.png

backup_pic.png


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