Lab 3 - EE 421L 

Authored by Michael Villalba,

villalb5@unlv.nevada.edu

9-29-2014 

  

Layout a 10-bit digital-to-analog converter (DAC)

In this lab we will be making layout for the 10-bit DAC we created in Lab 2.  By following tutorial 1 we will build the 10k resistor layout and then will use that resistor in our layout for the 1-bit DAC.

The first thing we need to do is copy all the cells from library Lab 2 into a new library that we will create called Lab3 so thatwe can compare results between the two.


CopyLab2.png


Then we will need to create a layout cell called  R_n_well_10k to create the 10k resistor. 


R_n_well_10k_cell.png

Once the layout opens create a rectangle using the n-well layer. (It doesnt matter how you lay it out because we will be making modifications to it.)


n_well_rectangle.png


Now we need to make our modifications to our rectangle using the MOSIS design rules, because we are using the C5 process we will be using lambda as .3u (300nm). We also find from the design rules that there needs to be a minimum width of (12)lambda and a spacing of (18)lambda.

12xlambda = 3.6um

18xlambda = 5.4um


From the MOSIS sheet we see that the sheet resistance of a n-well is 800 squares.

To find a length and width that satisfies the design rules we can use the resistance formula to find our dimensions.

R = Rsquare *(L/W)


R= 10k, Rsquare = 800, and use W = 3.6um

Thus giving us L = 45um


n_well_parameters.png

Now test to see if our parameters pass the DRC.


DRC.png

It does so we are okay to continue. We now need to add a n-tap on each end of the n-well rectangle. We can find n-tap in the NCSU_Techlib_ami06 and place on either side of the n-well.

n_tap.png


 DRC once again to make sure there were no problems. Now we are going to add the pins at the end of the resistor to be connected. Choose metal 1 and create a pin over the n-tap giving the pin names L for metal1 that covers the left n-tap and repeat for the right n-tap.

Metal1_connection.png


Next DRC for no error issues. Now we will need to place the final layer over the resistor. Select Res_id and draw a rectangle that covers the n-well rectangle completely.

Res_id.png

 

After doing a DRC for the final time we will extract the layout to see the given resistance of the layout which should be approximately 10k.

Extract.png

Now we will create a resistive divider as explained in tutroial 1. Create a layout R_2R and insert three 10k n-well resistors that we just previously created with proper spacing that follows the MOSIS design rules.

R_2R_with_3_n_wells.png

Spacing.png

Next we are going to connect metal1 layers and draw some rectangles to connect the resistors together in series.

Resistor_connect.png

Now create some pins over the rectangles. These pins will be exactly the same as R_2R schematic. We will be giving the top left metal1 rectangle pin name 'in', then top for the metal1 rectangle that connects the middle resistor to the bottom resistor 'top', then name the bottom rectangle 'bottom'.

Res_pins.png

Then DRC to make sure there were no connection errors. Save and do an LVS to make sure the layout matches the schematic we made in Lab 2.

LVS.png

We then get then get the notification that it is a match.

Last thing to do is to make sure to back up our work

backup.png


Return to EE 421L Labs