Lab 6 - EE 421L 

Authored by Nha Tran

Email: trann4@unlv.nevada.edu

NHSE ID: 2000590233

10/20/2014 

  

Lab objective: The purpose of this lab is to design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

 

Prelab:
First create a backup of the work that was done previously in the class and lab by typing tar -cvf backuplab6.tar CMOSedu/ in the MobXterm command line. this command line back-ups all the data that is in the CMOSedu/ folder up until lab 6. Then send a copy of the backup to your email. Then go through tutorial 4 located in the CMOSedu.com website.

LAB:
 
First draft the schematic of the nand gate as seen below.
ntlab6_01.PNG
 
Next create a symbol of the nand gate by going to cellview create cellview and delete everything and redraw the symbol similar to the one below.
ntlab6_02.PNG
   
Next draft the following layout for the nand gate, then DRC to show that it has no error
ntlab6_03.PNG
   
Lastly extract the layout and LVS it to make sure that it matches the schematic.
ntlab6_04.PNG
   
next draft the schematic like below so we can test the function of our nand gate
ntlab6_05.PNG
   
ADE and choosing a transient analysis of 25ns and choosing to plot A, B and out.
ntlab6_06.PNG
   
Looking at the graph we can see what when A,B = 00, 01, and 10, the output is 1 and when A,B = 11 the output is 0, this matches the truth table for a nand gate so we know that our nand gate schematic works. at the transition when A and B switches from 0 to 5V, the output is not smooth because there is a time difference between the input A and B.
   
       
next draft a schematic of a Xor gate like below.
ntlab6_07.PNG
   
now create a new symbol for the xor gate similar to the one seen below
ntlab6_08.PNG
   
next create a layout of the xor gate like below. and DRC it to make sure that there is no error.
ntlab6_09.PNG
 
next extract the layout and LVS it to make sure that it matches our schematic.
ntlab6_11.PNG
   
Lastly create the following schematic to test our xor gate.
ntlab6_12.PNG 
   
Looking at the graph we can see that when A,B = 00, 11 the output is 0, and when A,B = 01, 10 the output is 1. This indicate that our Xor gate works the way it is suppose to work. The output has moments where it is not straight this is cause by the difference in the Nmos and Pmos that is used in xor gate. the transistion where the A and B switches from 0 to 5v. there is a delay between A and B and this cause the output to not be a flat line.
   
Next before we make the schematic for the full-adder, we will make a circuit that will impliment the inverter, nand, and xor gate.
ntlab6_21.PNG
   
As you can see from the graph all 3 logic gates works the way it is suppose to. there is a slight delay in each of the logic gates, this is cause by the time it takes for the voltage to reach the gates. from the graph xor had a slight dip when both A and B changes simultaneously. if the period of the input were shorter this will cause an error in the reading because that dip would look like it have a false output. Other than that everything is working fine. however if our circuit contain multiple gates that goes to the same output and the gates for A and B is not equal when we reach the output, than it will cause the same delay problem. Because the xor gate is bigger in size compared to the nand gate it would be logically to think that there is a bigger time delay to reach the output in the xor gate than the nand gate.
ntlab6_22.PNG


   
Next we will draft the schematic for a full-adder by connecting our nand and xor gate like below.
ntlab6_13.PNG
 
Next we create a symbol for the full-adder like below.
ntlab6_14.PNG
   
Next create a layout of the full-adder like below. then DRC it and make sure it have no error. ntlab6_15.PNG
   
next extract the layout and LVS it with the schematic to make sure they match.ntlab6_16.PNG
   
lastly draft the schematic as shown below to simulate the full adder.
ntlab6_18.PNG
   
Cin, A, and B should be an 8-bit input while S and Cout should be the output. the following table shows how the graph should be if it matches.
ntlab6_17.PNG
 
As you can see the graph matches the truth table. when A,B and Cin = 111, the Cout and S =1, when A,B, Cin = 110, Cout is 1 while S =0, along with all the other input from 000 to 111 the output matches the truth table indicating that our full-adder works.
ntlab6_19.PNG


lastly zip up everything and email to self.
ntlab6_20.PNG


link to lab6.zip folder where the schematic, layout, and symbol are located
   
   

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