Lab 4 - EE 421L 

Authored by Brian Smith (smith945@unlv.nevada.edu),

October 13th, 2014

The goal of this lab is to create two inverters, schematics and layout, and simulate them using both Spectre and UltraSim. One using PMOS and NMOS sizes of 12u/600n and 6u/600n, respectively. The other uses sizes of of 48u/600n and 24u/600n by using a multiplier of 4.

To start off, I created a schematic for the first two inverters. These can be seen below (12u/6u nmos/pmos widths on left, 24u/48u on right):

Next, I created a layout for both of these. The first used a normal NMOS and PMOS with widths/lengths of 6u/600n and 12u/600n, resptectively. The second is similar, but has the widths being effectively 4 times as large by using 4 "fingers" of poly.This can be seen below (6u/12u width nmos/pmos on left):

I ensured that the layout had the correct pins to align with my schematic so that I could run a LVS. I first ran a DRC, which was successful as seen below:

Then, I ran a LVS to ensure that I made no errors in the layout with respect to connections conforming to the schematic. Both of these ran sucessfully. The setup and outputs are shown below, first for the inverter with 6u/12u width NMOS/PMOS devices:

The setup and output for the layout with 24u/48u width NMOS/PMOS devices:

In order to simulate these, I created a symbol for both inverters. These are shown below:

Then two schematics were created to simulate the output of the inverters. I set them up to use a 5V power source and a a 0V-5V square wave with a 1ns rise time. There is a capacitive load with a variable CapLoad so that I can simulate multiple values in one simulation. The schematics for both inverters are shown below:

With that completed, I moved on to simulating the inverters for capacitive loads of 100fF, 1pF, 10pF, and 100pF. Firstly by using Spectre to do the simulation. To do that I had to open up the ADE and set up the model libraries as shown below:

My simulation was then set up as shown below for a transient analysis (this is identical for both inverters):

Now, I set up a parametric analysis in order to simulate the capacitive loads in one graph for each inverter.

Running that gave me the output for all loads. The input is shown in a dotted line. The values of the load capacitance is shown on the left in the "CapLoad" column.

First, the inverter with 6u/12u width NMOS/PMOS transistors:

Then the inverter with 24u/48u width NMOS/PMOS transistors:

I then set up the simulation to use ultrasim and pointed to the correct model files for it to use. Running the simulation, these are the resulting outputs:

First, the inverter with 6u/12u width NMOS/PMOS transistors:

Then the inverter with 24u/48u width NMOS/PMOS transistors:

The output looks very similar, although the curves in the UltraSim outputs seem less smooth (most notably, the green 10pF line for the 24u/48u inverter, which also doesn't reach the same minimum point as the Spectre output).

That concludes laboratory 5. My library backup for this lab is located here.

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