Lab 5 - EE 421L 

Authored by Henry Chan,

chanh6@unlv.nevada.edu

October 13, 2015

This lab will examine inverters using schematics, layouts, and symbols with NMOS and PMOS transistors.

Two inverters having sizes of:

12u/6u, (meaning the width of the PMOS / width of the NMOS where both devices have minimum lengths of 0.6u)

and

48u/24u, where devices use a multiplier, M=4.

The inverter works by configuring the MOSFET positions in such a way that a voltage being applied to the gates of both the NMOS and PMOS will result in an opposite output. This is done by attaching the source of the PMOS to VDD and the source of the NMOS to ground, then connecting the drain of the PMOS to the drain of theNMOS. The base or bulk of either MOSFET is connected to their respective sources. When the input is high, the NMOS device will tie the output to ground and when the input is low, the PMOS device will tie the output to VDD, thus successfully functioning as an inverter.

I begin by creating the schematic, layout and symbol for each inverter.

12u/6u Inverter

I create the shematic using the nmos4 and pmos4 instances found in the NCSU_Analog_Parts library.

A symbol may be created from the cellview by clicking Create->Cellview->From Cellview

Deleting everything except for the pins allows us to draw the following symbol.

After the schematic and symbol are made, the layout may be produced.. Instances from the NCSU_TechLib_ami06 library were used to create the nmos and pmos layouts along with ntap and ptap instances. Width and length were adjusted accordingly and metal layers were connected to create the following.

A represents the input and Ai represents the output

The power is run on the top of the cell using metal1 and ground is run on the bottom of the cell using metal1 as well.

Power (vdd!) is connected to the n-well using the ntap cell.

Ground (gnd!) is connected to the p-substrate using the ptap cell.

The layout LVS checks out.

48u/24u Inverter

I copied the previous schematic to another cell view called not4 and used it as a template to produce the 48u/24u inverter. Simply by editing the properties of the transistors ('Q') and modifying the multiplier to 4, the 48u/24u inverter was created.

Using the same method as before, a successful symbol was created for the 48u/24u inverter.

The layout was then produced with the appropriate nmos and pmos characteristics from the NCSU_Techlib_ami06 library. Ntap, ptap, and metal1 connections were added to produce the 48u/24u inverter.

LVS was completed successfully.

Now that the components are created, it is time to simulate the devices.

12u/6u Inverter - 1pF Capacitive Load

12u/6u Inverter - 10pF Capacitive Load

12u/6u Inverter - 100pF Capacitive Load

The simulation results are very telling when increasing the capacitive load to the inverter. As you raise the capacitance, the output begins tobehave less like an inverter and seems increasingly unresponsive to the input voltage.

48u/24u Simulations

Now that we've examined the 12u/6u inverter, it is time to examine the 48u/24u inverter.

The simulation schematic was easily created by copying the 12u/6u schematic and simply changing the inverter to the 48u/24u inverter.

Opening the ADE window again will allow us to produce the simulations. (Don't forget to include the model libraries!)

48u/24u Inverter - 100fF Capacitive Load

48u/24u Inverter - 1pF Capacitive Load

48u/24u Inverter - 10pF Capacitive Load

48u/24u Inverter - 100pF Capacitive Load

As you can see, the 48u/24u while still suffering from unresponsiveness, still performs slightly better than its 12u/6u counterpart.

Up to this point, all simulations have been run using spectre, however, sometimes it is appropriate to use UltraSim, a faster, but less accurate simulator found. (UltraSim is typically used for larger circuits for its fast simulation times)

With the ADE window selected, click Setup -> Simulator/Directory/Host -> and select UltraSim similar to the image below.

(Don't forget to setup the model libraries!)

12u/6u Inverter - 100fF Capacitive Load (UltraSim)

12u/6u Inverter - 1pF Capacitive Load (UltraSim)

12u/6u Inverter - 10pF Capacitive Load (UltraSim)

12u/6u Inverter - 100pF Capacitive Load (UltraSim)

48u/24u Inverter - 100fF Capacitive Load (UltraSim)

48u/24u Inverter - 1pF Capacitive Load (UltraSim)

48u/24u Inverter - 10pF Capacitive Load (UltraSim)

48u/24u Inverter - 100pF Capacitive Load (UltraSim)

End of Lab 5

Files from this lab may be found here.

Backups were made using cloud storage.

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