Lab 5 - ECE 421L 

Elizabeth Baldivias

baldivi3@unlv.nevada.edu

Design, layout, and simulation of a CMOS inverter.

Pre-Lab

    - Back up all lab work.
    - Go through tutorial 3.

Going through tutorial 3 will be explained below:
 
To create an inverter a PMOS4 of dimensions 12u/6u and NMOS4 of dimensions 6u/6u are used. Labels are created with input A and output Ai.

The following images prove that the LVS passed and the schematic and layout correspond.

Using stimuli as directed in the tutorial, giving a dc analysis and sweeping V0 will give the following launcher.

Hitting run on the simulation gives the following output.

End of Pre-Lab.

Lab

Draft schematics, layouts, and symbols for two inverters having sizes of:

   - 12u/6u

   - 48u/24u where the devices use a multiplier, M=4.

To create the 12u/6u inverter, the inverter from the Pre-Lab was used by making a copy into the Lab5 directory. A symbol was made based on the inverter schematic.
 
 
 
A copy of the inverter layout was made into the Lab5 directory. The extracted image is shown below.
 
         
 
After creating the layout and the extracted views, the following step was to LVS the schematic vs the extracted cells. Following are the images proving that these cells match.
 
   
 
Now that the 12u/6u inverter was made, the next step was to make the 48u/24u inverter. In the schematic this was made simply by changing the multiplier "m:" to 4 instead of 1. The symbol was changed to edit the text to "48u/24u".
 

 
The layout was changed by going to the paramaters of the NMOS and PMOS and changing the multiplier to 4. For the ntap and ptap the columns of contact changed to 8 and the rows of contact changed to 2. Edits were made to pin names gnd!, vdd! and Ai to match the new sizes of the different parts. Poly1 rectangles and metal1 rectangles were added to the corresponding layers. All this gave the layout and extracted view below.
 
   
 
Once the layout was done, the next step was to LVS the schematic and the extracted and make sure they match.
 


 
The next step of the lab was to create a schematic to simulate the inverter with vpulse with a transient analysis of 25 ns, the 12u/6u inverter symbol and different values of capacitors 100fF, 1pF, 10pF, and 100pF.
 
Here is the schematic that was used. The rest of the schetics were the same except for the different value capacitor.
 

 
Output of 100fF

 
Output of 1pF

 
Output of 10pF

 
Output of 100pF

 
Comment on the result.
As the capacitor value increases the output behaves less like an inverter. It becomes very unresponsive to the input.
 

The next part of the lab requires to simulate the 48u/24u inverter. Using a vpulse with a transient analysis, the inverter symbol, and capacitors of 100fF, 1pF, 10pF, and 10pF, created the following schematic,

(the capacitor values will change for each of the following outputs)

Output 100fF

Output 1pF

Output 10pF

Output 100pF

Comment on the result.

The 48u/24u responds better to the higher capacitor loads than the 12u/6u inverter. In the end it is still affected by the capacitor load in that the higher the load, the less the output behaves as an inverter. 

The next part of the lab was to run the simulations with UltraSim which is Cadence's fast SPICE simulator for larger circuits at the cost of accuracy.

To simulate using UltraSim go to Setup-> Simulatior/Directory/Host and select UltraSim.

Running the 12u/6u simulations using UltraSim gives the following:

Output 100fF

Output 1pF

Output 10pF

Output 100pF

UltraSim for 48u/24u inverter.

100fF

1pF

10pF

100pF

To create backups of the lab work a zip was done on the Lab5 directory in the virtaul environment. Lab5_EB.zip contains all of the cadence directories.

To create a backup of the webpage directory a zip was done to create LAB5_htmlpage.zip.

An upload of both directories was made to EE421L google drive directory.

Click here for Lab5_EB.zip

 Return to EE421 labs here.