Lab Design Project, Part 2 - EE 421L 

Project description:

The first part of this project was creating a schematic of a simple

ALU. Part 2 is the layout of that schematic.

The four functions are AND, OR, ADD, and SUB, and are selected with the two-bit F input.

F[0] is least significant bit, or LSB.

F[1] is most significant bit of control signals (MSB).

No major changes were made to the schematic, which is presented below for convienience.

The general layout is presented below:

The annotation text is clearer if subcell layouts are hidden when viewing. A few detailed views are presented below.

First, the connections between the AND and OR gate arrays and the MUX that selects the output. Note that the

bus inputs generally run horizontally on metal3, with vertical runs of metal2 for connections into the cells. The leaves

metal1 available for a  horizontal bus on the top, and metal2 for a horizontal bus below.

One final region to discuss is the inverter on the B bus before it gets to the adder. As noted in the picture,

the three different layers really help the circuit designer increase density. Obviously, having 6 or 7 layers

would greatly ease the difficulty of routing large 32 and 64 bit busses, and perhaps even leave room for shielding

between layers of so-called "noisy" digital signals.

This concludes our project.
 

The .jelib file can be found here

Bakup files: (multiple copies of proj2.htm)

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