Lab

Lab 6 - ECE 421L

Authored by Carlo Lopez-Tello.

Email: lopeztel@unlv.nevada.edu.

October 14, 2013.

Lab Description:

In this lab we will layout different logic gates and a full adder.

First, make a NAND gate. A NAND gate consist of two NMOS and two PMOS in the following configuration.

Make the following symbol to represent a NAND gate.

Finally, proceed to make the following layout.

Check your layout: DRC, NCC, and ERC.

Now, we are going to simulate the operation of the gate using PSPICE.

Create a new schematic.

Make sure to increase the input voltages to make a display a better graph. Just add multiples of 6 to the inputs.

Now simulate the NAND gate using IRSIM.

Make a NOR gate. A NOR gate consist of two NMOS and two PMOS in the following configuration.

Make the following symbol to represent a NOR gate.

Finally, proceed to make the following layout.

Check your layout: DRC, NCC, and ERC.

Now, we are going to simulate the operation of the gate using PSPICE.

Create a new schematic.

Make sure to increase the input voltages to make a display a better graph. Just add multiples of 6 to the inputs.

Now simulate the NOR gate using IRSIM.

Make a XOR gate. A XOR gate consist of six NMOS and six PMOS in the following configuration.

Make the following symbol to represent a XOR gate.

Finally, proceed to make the following layout.

Check your layout: DRC, NCC, and ERC.

Now, we are going to simulate the operation of the gate using PSPICE.

Create a new schematic.

Make sure to increase the input voltages to make a display a better graph. Just add multiples of 6 to the inputs.

Now simulate the XOR gate using IRSIM.

With these gates we can make a full adder. Make a new cell named full adder and using your gates build it.

Create the following symbol for the adder.

Create a new cell and simulate the full adder.

We can also make a Full adder using only NAND and XOR gates. Create a new cell and implement the followung circuit.

Use the following symbol.

Now layout the adder.

Check your layout: DRC, NCC, and ERC.

Now, we are going to simulate the operation of the adder using PSPICE.

Create a new schematic.

Make sure to increase the input voltages to make a display a better graph. Just add multiples of 6 to the inputs.

Now simulate the adder gate using IRSIM.

Backup your work.