Lab 7 -
EE 421L
Authored
by Min Lan,
LANM2@UNLV.NEVADA.EDU
10/18/2013
Electric library: ML_ee421L_f13_lab7.jelib
Lab
description
In this lab, we will draft the schematics of 8-bit NAND, NOR, AND, and OR gates,
using buses. We will also draft MUXes, DEMUXes, Full Adder, and 8-Bit Adder; they
will be used in the ALU for the project. The layout for 8-Bit Adder will also be drafted.
8-bit NAND gate array
Schematics
8-bit NOR gate array
Schematics
8-bit AND gate array
Schematics
8-bit OR gate array
Schematics
2-to-1 DEMUX
Schematics
8-bit 2-to-1 DEMUX/MUX
Schematics
![images/8_bit_mux_2_1_sch.jpg](images/8_bit_mux_2_1_sch.jpg)
![images/sim_8_bit_mux_2_1_sch.jpg](images/sim_8_bit_mux_2_1_sch.jpg)
- Simulate with LTspice
![images/sim_8_bit_mux_2_1_spice.png](images/sim_8_bit_mux_2_1_spice.png)
- Simulate with IRSIM
![images/sim_8_bit_mux_2_1_IRSIM.jpg](images/sim_8_bit_mux_2_1_IRSIM.jpg)
Full Adder
Schematics:
- Arc names are used to connect inputs for clean look
![images/full_adder_sch.png](images/full_adder_sch.png)
Layout:
![images/full_adder_lay.png](images/full_adder_lay.png)
- NCC, DRC, ERC checks:
![images/full_adder_lay_checks.png](images/full_adder_lay_checks.png)
8-bit Adder (2)
Schematics:
Simulation with IRSIM:
![images/8_bit_adder_sch_IRSIM.png](images/8_bit_adder_sch_IRSIM.png)
- 5 + 3 = 8
- 2 + 7 = 9
Layout:
- Overview
![images/8_bit_adder_lay2.png](images/8_bit_adder_lay2.png)
- One Level Down
![images/8_bit_adder_lay.png](images/8_bit_adder_lay.png)
- DRC, NCC, ERC checks
![images/8_bit_adder_lay_checks.png](images/8_bit_adder_lay_checks.png)
Backup
Zip both your library file and your webpages and email to yourself.
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