Lab 3 - EE 421L 

Vallesm, Mario

vallesm@unlv.nevada.edu

2/20/2015

                    Opamps 1

        basic topologies, finite gain, and offset

    experiment 1

The experimentation was performed in the following Circuit whttp://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/circuit1.PNG

a)http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00002.PNG
b)

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00003.PNG

                    Vcc = 5V and Vdd = 0 and also the DC offset is 2.5 V

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00005.PNG

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00004.PNGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/Circuit%20lt%20sprice.PNGhttp://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/datapoint.PNG

Explain how the following circuit can be used to measure the op-amp's offset voltage

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/Circuit2.PNG

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00006.PNG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00007.PNG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00008.PNG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/TEK00009.PNG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%203/offset_voltage.PNG

Return to Labs