EE 420L - Lab 8

Characterization of the CD4007 CMOS transistor array 

 

Authored by Nicholas Moya

April 16th, 2015

moyan1@unlv.nevada.edu

  

The purpose of this lab is to collect experimental data of the transistors used in the CD4007.pdf CMOS transistor array, use that data to make parameters for simulations in LTspice and compare the simulations with experimental data. After comparison, we can augment our parameters to better simulate our experimental results.

 

Experimentally generate, for the NMOS device, plots of: 

1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 

2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and 

3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 

 

1) Experiment NMOS

 

IMG_20150410_092318_203.jpg

Scope reading

 

2) Experiment NMOS

 

 IMG_20150410_101253_813.jpg

  VGS = 1V

 

 IMG_20150410_101308_249.jpg

 VGS = 2V

 IMG_20150410_101334_811.jpg

 VGS = 3V

 

 IMG_20150410_101402_384.jpg

 VGS = 4V

 

 IMG_20150410_101424_650.jpg

 VGS = 5V

 

 

3) Experiment NMOS

 

 IMG_20150410_094635_240.jpg

 VBS = 0

 

 IMG_20150410_095524_016.jpg

 VBS = 1

 

 IMG_20150410_095623_562.jpg

 VBS = 2

 

IMG_20150410_095705_541.jpg

 VBS = 3

  

1) Experiment PMOS

 

 1.JPG

 

3) Experiment PMOS

 

 3.JPG

 VSG = 5V

 

 IMG_20150410_111204_434.jpg

 VSG = 4V

 

 IMG_20150410_111234_490.jpg

 VSG = 3V

 

 5.JPG

 VSG = 2V

 

 6.JPG

 VSG = 1V

 

 

 

3) Experiment PMOS

 

Assuming that the length of the NMOS is 5 um and its width is 500 um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF.

 

7.JPG

 

From this data, we create a LTspice model with the following parameters:

 

 .MODEL N_level1 NMOS LEVEL = 1
+ TOX    = 1.13E-14
+ VTO    = 0.8
+ GAMMA  = 1
+ KP     = 9.38E-6
*
.MODEL P_level1 PMOS LEVEL = 1
+ TOX    = 1.13E-14
+ VTO    = 0.8
+ GAMMA  = 1
+ KP     = 4.8E-6

 

Using these models, we recreate the 3 experiments in simulation and gather our results.

 1) Simulation NMOS

 

1_nmos_schematic.PNG     1_nmos_simulation.PNG

 Schematic                                             Simulation

 

2) Simulation NMOS

 

2_nmos_schematic.PNG

Schematic

2_nmos_simulation_1_5.PNG

VGS = 1V

2_nmos_simulation_2_5.PNG

VGS = 2V

2_nmos_simulation_3_5.PNG

VGS = 3V

2_nmos_simulation_4_5.PNG

VGS = 4V

2_nmos_simulation_5_5.PNG

VGS = 5V

 

3) Simulation NMOS

 

 3_nmos_schematic.PNG

 Schematic

 3_pmos_simulation_1_4.PNG

 VGS varied 0 to 3 V (VSB = 0) 

 

 3_nmos_simulation_2_4.PNG

 VGS varied 1 to 4 V (VSB = 1)

 

 3_nmos_simulation_3_4.PNG

 VGS varied 2 to 5 V (VSB = 2)

 

 3_nmos_simulation_4_4.PNG
VGS varied 3 to 5 V (VSB = 3)

 

 1) Simulation PMOS

 

1_pmos_schematic.PNG 

 Schematic

 

1_pmos_simulation.PNG

 Simulation

 

 2) Simulation PMOS

 

 2_pmos_schematic.PNG

 Schematic

 

 2_pmos_simulation_1_5.PNG

 VSG = 1V

 

 2_pmos_simulation_2_5.PNG

 VSG = 2V

 

 2_pmos_simulation_3_5.PNG

 VSG = 3V

 

 2_pmos_simulation_4_5.PNG

 VSG = 4V

 

 2_pmos_simulation_5_5.PNG

 VSG = 5V

 

3) Simulation PMOS

 

 3_pmos_schematic.PNG

 Schematic

 

3_pmos_simulation_1_4.PNG

VSG varied 0 to 3 V (VBS = 0)

 

 3_pmos_simulation_2_4.PNG

VSG varied 1 to 4 V (VBS = 1)

 

 3_pmos_simulation_3_4.PNG

 VSG varied 2 to 5 V (VBS = 2)

 

 3_pmos_simulation_4_4.PNG

VSG varied 3 to 5 V (VBS = 3)

 

 Inverter - Using the chip, we can also build an inverter. The simulation data is provided below:

 

 inverter.jpg

 Inverter schematic

 

 inverter.jpg

 Simulation part 1

 

 inverter_sim_2.jpg

 Simulation part 2

 

 This is the experiemtal data provided from the scope readings:

 

 8.JPG

 Vin = Yellow (rising), Vout = Blue (falling)

 

 9.JPG

 Vin = Yellow (falling), Vout = Blue (rising)