Lab 8 - EE 420L Engineering Electronics II 

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu

March 20th, 2015 

  

Characterization of the CD4007 CMOS transistor array


 Pre-lab work
Lab Description
In this lab you will characterize the transistors in the CD4007 and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply. In other words, don't characterize the devices at higher than +5 V voltages or lower than ground potential.
    1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 
    2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and 
    3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 

Lab Data
                  
NMOS Experiment 1
    Using a sample resistor of 100 Ohms


NMOS Experiment 2 using a sample resistor of 200 Ohms
     VGS = 1V

    VGS = 2V

    VGS = 3V

    VGS = 4V

    VGS = 5V

    VGS Combined


Experiment 3:


PMOS
Experiment 1: sample resistor = 200 Ohm

Experiment 2:


Experiment 3:


Hand Calculations


Basic Level = 1 MOSFET Model before modifications

After comparing my simulations to the experimental results, I observed that the simulations
current 'Id' was off by a factor of about 1.5 for the NMOS and that the bias voltage sim did
not completely match. I compensated for this error in the KP and Gamma value for NMOS. Similarly,
I changed the values of the PMOS KP to better match my experimental data. The new modified model
is provided here.

Sim Experiment 1 NMOS


Sim Experiment 2 NMOS


Sim Experiment 3 NMOS


Sim Experiment 1 PMOS


Sim Experiment 2 PMOS


Sim Experiment 3 PMOS


Inverter


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