Homework
assignments and Project Information for ECG 721 Memory Circuit Design, Spring 2024
HW#17 – A19.10 and A19.11, April 10
HW#16 – A19.2 and A19.3, April 3
HW#15 – A19.8 and A19.9, March 27
HW#14 – A19.6 and A19.7, March 25
HW#13 – A18.4 and A18.5, due March 20
HW#12 – A18.1 and A18.2, due March 18
HW#11 – A17.3, due March 4
HW#10 – A17.2 and A17.4, due February 28
HW#9 – A17.1, due February 26
HW#8 – A16.14 and A16.15, due February 21
HW#7 – A16.12, due February 14
HW#6 – A16.9–A16.10, due February 12
HW#5 – A16.6–A16.8, due February 7
HW#4 – A16.4 and A16.5, due February 5
HW#3 – A16.1–A16.3, due January 31
HW#2 – A11.1, A11.10, and A11.11, due Janaury 24
HW#1 – A10.1–A10.3, due January 22
Projects – You decide on a project subject, which must be approved by Dr. Baker (link). Some examples of topics include: 1)
design of all digital DLLs for use in SDRAM (include tutorial operation
of SDRAM followed by why a DLL is needed in an SDRAM), 2) the use and
design of synchronous mirror delays (what they are and how they work),
3) use of an over–damped PLL in place of DLL in SDRAM. Is this possible
or practical? What are the benefits and drawbacks?, and 4) the use of
self–biasing in the design of PLLs and DLLs,design of analog PLLs, a tutorial overview .
I would prefer you come up with your own project topic since these are
topics that were used in the previous times I taught this course.
***A presentation, in PDF format, is due to Dr. Baker at r.jacob.baker@unlv.edu by COB (close of business) on Monday, April 22, 2024.***