Homework
assignments and Project Information for ECE 572/472 Power Electronics,
Fall
2010
Homework
guidelines are found here.
Course
projects due Monday, November 29 – Suppose you work at a company that
makes
memory chips. To move ahead of the competition, and increase your
company’s
market share, an aggressive approach to reduce costs and chip power
consumption
is adopted. It’s decided that all of the voltage regulators and charge
pumps
will be removed from the memory chip. This simplifies the number of
steps used
to make the chips, reduces die size, and allows the use of dc-to-dc
converters
having > 90% efficiencies ultimately reducing the power consumed
by memory
system. With this change, however, the cost of the DC-to-DC converter
is added
to the cost of a memory module.
Your
project is to design a DC-to-DC converter, using the relatively
low-cost C5
process that accepts an input voltage ranging from 3 to 5 V and
generates
output voltages of 1.25 and 2 V at 100 mA each (max). For graduate
students,
those enrolled in ECE 572, also design a converter to generate -500 mV
at 100 uA (max).
Your report
should detail your design concerns and reasons for the design
selections,
simulations showing performance with varying loads and input voltages,
efficiency, and temperature performance. Make sure all top-level
simulations
are done with a single icon with input VDD and outputs 1.25 and 2 V
(and -500
mV if a graduate student).
Email me a
PDF of your report and your simulation design directory zipped up
(e.g.,
jakebaker_ECE_5472_project.rar) before the start of class on Monday
November
29.
Note that
some of the blocks in the design will be provided for you (e.g., the
transistor
design of a bandgap to generate the 1.25 V reference voltage, op-amp,
ramp
generator, comparator, etc.).
HW#
18 due Friday, December 10 – Do Example 8-10 using LTspice.
HW#
17 due Monday, December 6 – problem 7-1. Verify your answers using
LTspice.
HW#
16 due Friday, November 5 – book problems 9-8 and 9-9. Also, verify
your hand
calculations with simulations.
HW#
15 due Monday, November 1 – design (select the duty cycle, filter
inductor/capacitor) and simulate the operation of a ZCS converter using
the
parameters given in Ex. 9-1 with an output voltage of 6 V (6 ohm load).
HW#
14 due Friday, October 29 – book problems 7.24 and 7.25
HW#
13 due Friday, October 22
1.
Show, using hand
calculations and LTspice
simulations, the challenges with using a Type-I error amplifier (the RC
integrator) to stabilize a power supply control loop employing PWM.
Assume the
Buck converter of Example 6-1 is being controlled (you get the filter
and load
values from this example then discuss how to select the RC of the
integrator).
Note that if you want you can include the gain of the PWM (= 1/Vp) by putting a
voltage-controlled voltage source in
between the integrator and filter with its value set to 1/Vp
(say Vp = 50). Your
solution should show the
hand-calculated location of the poles, a Bode plot, and then LTspice
verification
of your Bode plot.
2.
Repeat part 1 using a
Type-II error
amplifier
HW#
12 due Friday, October 15 for the feedback system seen in Fig. 7-18b
determine
the gains of each block (assume a simple RC integrator for the error
amplifier
block) and verify your hand calculations with simulations. Make sure
your hand
calculations and LTspice verifications are simple and easy to follow.
Assume a
Buck converter is used in the design.
HW#
11 due Monday, October 11
1.
Using the C5 process
design a Buck
converter that can supply 1.5 V @ up to 1 A from a 5V source. Assume
your
circuit inputs are 5V, ground and a 0 to 5V clock at 5 MHz. Make a
symbol for
your design that can be used for simulations. Note the symbol will have
3 pins
(VDD, Clock, and Vo). Determine the efficiency of your design
((Vo*Io)/(Vs*Is)
under full load conditions (the converter supplying 1 Amp). What is the
minimum
current your converter can supply while maintaining the output voltage
at 1.5V?
2.
Verify, with
simulations, the results of
Example 6-9.
HW#
10 due Wednesday, October 6 – book problem 6-35. Verify your answer
with
LTspice
HW#
9 due Monday, October 4 – book problems 6-29 and 6-31.Use LTspice to
simulate
the operation of the converters.
HW#
8 due Friday, September 24 – Using On’s
C5 process design
a Boost converter powered with VDD = 3.3 V that has an output voltage
of 5 V
with ripple less than 10 mV and that can supply 10 mA to a load. Again,
as in
HW# 7, a 10 MHz clock signal is available. However, in this design, the
clock
signal’s amplitude is 3.3 V (again you set the duty cycle). Simulate
your
design with the conditions described in HW# 7.
HW#
7 due Monday, September 20 – the SPICE MOSFET models for On Semiconductor’s
C5 process (information
from MOSIS) are found
in C5_models.txt. Using
the transistors in this C5
process design a Buck converter to supply 10 mA of current at 2 V if
the
converter is powered with 5 V and a 10 MHz clock signal is available
(you set
the duty cycle). Assume the maximum ripple allowed in the output
voltage is 10
mV. Simulate your design using LTspice showing, start-up and
steady-state
operation for no-load, 1 mA load, and full-load operating conditions.
Also show
how your design behaves (how the output voltage changes) if the load is
a
square wave of current varying from 0 to 10 mA at 100 kHz.
HW#
6 due Friday, September 17 – 6-1, 6-3, and 6-4 (use LTspice to verify
your
solutions in 6-4)
HW# 5 due Monday, September
13
HW# 4 due Friday, September
10
HW# 3 due Friday, September
3
HW#
2 due Wednesday, September 1 – Using a +9V supply connected to a 1 H
inductor
with the other side of the inductor connected to the IRF150 (IRF1503S
in
LTspice built-in models) to ground (just like discussed in class) show,
and
verify with LTspice, how:
1.
it’s possible to
generate voltages much
greater than +9 V using this circuit
2.
to limit the voltage
across the MOSFET
using a diode
3.
to calculate the
current flowing in the
inductor over time when the IRF150 is on
4.
to calculate the
energy stored in the
inductor (again, verify all with LTspice)
HW#
1 due Monday, August 30
1.
Show how to determine
the Fourier Series
representation of the waveform seen in Fig. 1-5 and how it can be used
to
determine the DC value of the voltage waveform?
2.
Show, using LTspice,
that a bipolar
junction transistor (BJT) can have a reverse recovery time just like a
diode.
Use the 2N3055 (built-in model in LTspice). Make sure you add a
resistor in
series with the collector and base while grounding the emitter.
3.
Simulate the operation
of the circuit seen
in Fig. 1-5 using an ideal switch if the switch is closed for T/4
instead of
T/3. Repeat the simulation with the positions of the resistor and
switch
swapped. Comment, in this second simulation, about the voltage across
the
resistor (note that if both sides of the resistor are at the same
potential
then the voltage across the resistor is zero).