*** SPICE deck for cell NAND_sim{sch} from library CMOSedu_9
*** Created on Sun May 27, 2007 10:56:01
*** Last revised on Sun May 27, 2007 11:00:52
*** Written on Sun May 27, 2007 11:01:09 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.OPTIONS NOMOD NOPAGE

*** CELL: NAND_2{sch}
.SUBCKT NAND_2 A AnandB B gnd vdd
** GLOBAL gnd
** GLOBAL vdd
Mnmos@0 AnandB A net@10 gnd NMOS L=0.6U W=3U
Mnmos@1 net@10 B gnd gnd NMOS L=0.6U W=3U
Mpmos@0 AnandB B vdd vdd PMOS L=0.6U W=3U
Mpmos@1 AnandB A vdd vdd PMOS L=0.6U W=3U
.ENDS NAND_2

*** TOP LEVEL CELL: NAND_sim{sch}
XNAND_2@2 A AnandB B gnd vdd NAND_2

* Spice Code nodes in cell cell 'NAND_sim{sch}'
.include C:\Electric\C5_models.txt
VDD VDD 0 DC 5
Vgnd GND 0 DC 0
Vb B GND DC 5
Va A GND DC 0 Pulse 0 5 1n 100p 100p 10n 20n
CL AnandB 0 300f
.tran 10p 50n
.END