*** SPICE deck for cell ring_osc_sim{lay} from library CMOSedu_6
*** Created on Wed May 23, 2007 16:31:54
*** Last revised on Wed May 23, 2007 16:34:10
*** Written on Wed May 23, 2007 16:36:20 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
***    P-Active:	areacap=0.9FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    N-Active:	areacap=0.9FF/um^2,	edgecap=0.0FF/um,	res=3.0ohms/sq
***    
*Polysilicon-1:	areacap=0.1467FF/um^2,	edgecap=0.0608FF/um,	res=6.2ohms/sq
***    Polysilicon-2:	areacap=1.0FF/um^2,	edgecap=0.0FF/um,	res=50.0ohms/sq
***    Transistor-Poly:	areacap=0.09FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    Poly-Cut:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=2.2ohms/sq
***    Active-Cut:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    Metal-1:	areacap=0.1209FF/um^2,	edgecap=0.1104FF/um,	res=0.078ohms/sq
***    Via1:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=1.0ohms/sq
***    Metal-2:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via2:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.9ohms/sq
***    Metal-3:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via3:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-4:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via4:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-5:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via5:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-6:	areacap=0.0423FF/um^2,	edgecap=0.1273FF/um,	res=0.036ohms/sq
.OPTIONS NOMOD NOPAGE

*** CELL: Inv_20_10{lay}
.SUBCKT Inv_20_10 In Out gnd vdd
Mnmos@0 Out In#1 gnd gnd NMOS L=0.6U W=3U AS=13.95P AD=7.762P PS=24.15U 
+PD=12.45U
Mpmos@0 Out In#3 vdd vdd PMOS L=0.6U W=6U AS=18.9P AD=7.762P PS=29.85U 
+PD=12.45U
** Extracted Parasitic Capacitors ***
C0 In 0 0.11fF
C1 Out 0 2.13fF
C2 vdd 0 0.54fF
C3 In#0 0 0.15fF
C4 In#4 0 0.29fF
C5 In#3 0 0.1fF
** Extracted Parasitic Resistors ***
R0 In#0 In#0##0 5.425
C6 In#0##0 0 0.073fF
R1 In#0##0 In#1 5.425
R2 In#3 In#3##0 6.717
C7 In#3##0 0 0.102fF
R3 In#3##0 In#3##1 6.717
C8 In#3##1 0 0.102fF
R4 In#3##1 In#4 6.717
R5 In#4 In#4##0 5.425
C9 In#4##0 0 0.073fF
R6 In#4##0 In#0 5.425
R7 In In##0 7.492
C10 In##0 0 0.114fF
R8 In##0 In##1 7.492
C11 In##1 0 0.114fF
R9 In##1 In#4 7.492
.ENDS Inv_20_10

*** CELL: ring_osc_21{lay}
.SUBCKT ring_osc_21 gnd osc_out vdd
XInv_20_1@0 osc_out#1 net@0 gnd vdd Inv_20_10
XInv_20_1@1 net@0 net@6 gnd vdd Inv_20_10
XInv_20_1@2 net@6 net@3 gnd vdd Inv_20_10
XInv_20_1@3 net@3 net@14 gnd vdd Inv_20_10
XInv_20_1@4 net@14 net@7 gnd vdd Inv_20_10
XInv_20_1@5 net@7 net@13 gnd vdd Inv_20_10
XInv_20_1@6 net@13 net@10 gnd vdd Inv_20_10
XInv_20_1@7 net@10 net@30 gnd vdd Inv_20_10
XInv_20_1@8 net@23 net@21 gnd vdd Inv_20_10
XInv_20_1@9 net@21 net@27 gnd vdd Inv_20_10
XInv_20_1@10 net@27 net@20 gnd vdd Inv_20_10
XInv_20_1@11 net@20 net@17 gnd vdd Inv_20_10
XInv_20_1@12 net@17 net@60 gnd vdd Inv_20_10
XInv_20_1@13 net@30 net@15 gnd vdd Inv_20_10
XInv_20_1@14 net@15 net@26 gnd vdd Inv_20_10
XInv_20_1@15 net@26 net@23 gnd vdd Inv_20_10
XInv_20_1@16 net@53 net@51 gnd vdd Inv_20_10
XInv_20_1@17 net@51 osc_out gnd vdd Inv_20_10
XInv_20_1@21 net@60 net@45 gnd vdd Inv_20_10
XInv_20_1@22 net@45 net@56 gnd vdd Inv_20_10
XInv_20_1@23 net@56 net@53 gnd vdd Inv_20_10
** Extracted Parasitic Capacitors ***
C0 osc_out#1 0 18.97fF
C1 net@0 0 1.93fF
C2 vdd 0 36.69fF
C3 net@6 0 1.93fF
C4 net@27 0 1.93fF
C5 net@20 0 1.93fF
C6 net@17 0 1.93fF
C7 net@60 0 2.03fF
C8 net@30 0 1.93fF
C9 net@15 0 1.93fF
C10 net@26 0 1.93fF
C11 net@23 0 1.93fF
C12 net@53 0 1.93fF
C13 net@51 0 1.93fF
C14 osc_out 0 19.49fF
C15 net@3 0 1.93fF
C16 net@45 0 1.93fF
C17 net@56 0 1.93fF
C18 net@14 0 1.93fF
C19 net@7 0 1.93fF
C20 net@13 0 1.93fF
C21 net@10 0 1.93fF
C22 net@21 0 1.93fF
** Extracted Parasitic Resistors ***
R0 osc_out#1 osc_out#1##0 8.661
C23 osc_out#1##0 0 18.033fF
R1 osc_out#1##0 osc_out 8.661
.ENDS ring_osc_21

*** TOP LEVEL CELL: ring_osc_sim{lay}
Xring_osc@0 GND osc_out VDD ring_osc_21
** Extracted Parasitic Capacitors ***
C0 GND 0 1.53fF
C1 osc_out 0 1.71fF
C2 VDD 0 1.46fF
** Extracted Parasitic Resistors ***

* Spice Code nodes in cell cell 'ring_osc_sim{lay}'
VDD VDD 0 DC 5
Vgnd GND 0 DC 0
.include C:\Electric\C5_models.txt
**.ic v(osc_out)=0
.tran 100p 30n
.END