*** SPICE deck for cell ring_osc_sim{lay} from library CMOSedu_6
*** Created on Wed May 23, 2007 16:31:54
*** Last revised on Wed May 23, 2007 16:34:10
*** Written on Wed May 23, 2007 16:34:39 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.OPTIONS NOMOD NOPAGE

*** CELL: Inv_20_10{lay}
.SUBCKT Inv_20_10 In Out gnd vdd
Mnmos@0 Out In gnd gnd NMOS L=0.6U W=3U AS=13.95P AD=7.762P PS=24.15U 
+PD=12.45U
Mpmos@0 Out In vdd vdd PMOS L=0.6U W=6U AS=18.9P AD=7.762P PS=29.85U 
+PD=12.45U
.ENDS Inv_20_10

*** CELL: ring_osc_21{lay}
.SUBCKT ring_osc_21 gnd osc_out vdd
XInv_20_1@0 osc_out net@0 gnd vdd Inv_20_10
XInv_20_1@1 net@0 net@6 gnd vdd Inv_20_10
XInv_20_1@2 net@6 net@3 gnd vdd Inv_20_10
XInv_20_1@3 net@3 net@14 gnd vdd Inv_20_10
XInv_20_1@4 net@14 net@7 gnd vdd Inv_20_10
XInv_20_1@5 net@7 net@13 gnd vdd Inv_20_10
XInv_20_1@6 net@13 net@10 gnd vdd Inv_20_10
XInv_20_1@7 net@10 net@30 gnd vdd Inv_20_10
XInv_20_1@8 net@23 net@21 gnd vdd Inv_20_10
XInv_20_1@9 net@21 net@27 gnd vdd Inv_20_10
XInv_20_1@10 net@27 net@20 gnd vdd Inv_20_10
XInv_20_1@11 net@20 net@17 gnd vdd Inv_20_10
XInv_20_1@12 net@17 net@60 gnd vdd Inv_20_10
XInv_20_1@13 net@30 net@15 gnd vdd Inv_20_10
XInv_20_1@14 net@15 net@26 gnd vdd Inv_20_10
XInv_20_1@15 net@26 net@23 gnd vdd Inv_20_10
XInv_20_1@16 net@53 net@51 gnd vdd Inv_20_10
XInv_20_1@17 net@51 osc_out gnd vdd Inv_20_10
XInv_20_1@21 net@60 net@45 gnd vdd Inv_20_10
XInv_20_1@22 net@45 net@56 gnd vdd Inv_20_10
XInv_20_1@23 net@56 net@53 gnd vdd Inv_20_10
.ENDS ring_osc_21

*** TOP LEVEL CELL: ring_osc_sim{lay}
Xring_osc@0 GND osc_out VDD ring_osc_21

* Spice Code nodes in cell cell 'ring_osc_sim{lay}'
VDD VDD 0 DC 5
Vgnd GND 0 DC 0
.include C:\Electric\C5_models.txt
**.ic v(osc_out)=0
.tran 100p 30n
.END