*** SPICE deck for cell ring_osc_sim{sch} from library CMOSedu_5
*** Created on Wed May 23, 2007 15:45:44
*** Last revised on Wed May 23, 2007 15:47:49
*** Written on Wed May 23, 2007 15:48:02 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.OPTIONS NOMOD NOPAGE

*** CELL: Inv_20_10{sch}
.SUBCKT Inv_20_10 In Out gnd vdd
** GLOBAL gnd
** GLOBAL vdd
Mnmos@0 Out In gnd gnd NMOS L=0.6U W=3U
Mpmos@0 vdd In Out vdd PMOS L=0.6U W=6U
.ENDS Inv_20_10

*** CELL: ring_osc_21{sch}
.SUBCKT ring_osc_21 osc_out gnd vdd
** GLOBAL gnd
** GLOBAL vdd
XInv_20_1@0 net@25 net@0 gnd vdd Inv_20_10
XInv_20_1@1 net@0 net@2 gnd vdd Inv_20_10
XInv_20_1@2 net@2 net@1 gnd vdd Inv_20_10
XInv_20_1@3 net@1 net@16 gnd vdd Inv_20_10
XInv_20_1@4 net@28 net@3 gnd vdd Inv_20_10
XInv_20_1@5 net@3 net@5 gnd vdd Inv_20_10
XInv_20_1@6 net@5 net@4 gnd vdd Inv_20_10
XInv_20_1@7 net@4 net@17 gnd vdd Inv_20_10
XInv_20_1@8 net@18 net@6 gnd vdd Inv_20_10
XInv_20_1@9 net@6 net@8 gnd vdd Inv_20_10
XInv_20_1@10 net@8 net@7 gnd vdd Inv_20_10
XInv_20_1@11 net@7 net@31 gnd vdd Inv_20_10
XInv_20_1@12 osc_out net@9 gnd vdd Inv_20_10
XInv_20_1@13 net@9 net@11 gnd vdd Inv_20_10
XInv_20_1@14 net@11 net@10 gnd vdd Inv_20_10
XInv_20_1@15 net@10 net@12 gnd vdd Inv_20_10
XInv_20_1@16 net@12 net@13 gnd vdd Inv_20_10
XInv_20_1@17 net@31 net@25 gnd vdd Inv_20_10
XInv_20_1@18 net@16 net@28 gnd vdd Inv_20_10
XInv_20_1@19 net@17 osc_out gnd vdd Inv_20_10
XInv_20_1@20 net@13 net@18 gnd vdd Inv_20_10
.ENDS ring_osc_21

*** TOP LEVEL CELL: ring_osc_sim{sch}
Xring_osc@0 osc_out gnd vdd ring_osc_21

* Spice Code nodes in cell cell 'ring_osc_sim{sch}'
VDD VDD 0 DC 5
Vgnd GND 0 DC 0
.include C:\Electric\C5_models.txt
**.ic v(osc_out)=0
.tran 100p 30n
.END