*** SPICE deck for cell inv_sim{lay} from library CMOSedu_3
*** Created on Tue May 22, 2007 16:43:54
*** Last revised on Wed May 23, 2007 09:33:00
*** Written on Wed May 23, 2007 09:33:33 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
***    P-Active:	areacap=0.9FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    N-Active:	areacap=0.9FF/um^2,	edgecap=0.0FF/um,	res=3.0ohms/sq
***    
*Polysilicon-1:	areacap=0.1467FF/um^2,	edgecap=0.0608FF/um,	res=6.2ohms/sq
***    Polysilicon-2:	areacap=1.0FF/um^2,	edgecap=0.0FF/um,	res=50.0ohms/sq
***    Transistor-Poly:	areacap=0.09FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    Poly-Cut:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=2.2ohms/sq
***    Active-Cut:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=2.5ohms/sq
***    Metal-1:	areacap=0.1209FF/um^2,	edgecap=0.1104FF/um,	res=0.078ohms/sq
***    Via1:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=1.0ohms/sq
***    Metal-2:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via2:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.9ohms/sq
***    Metal-3:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via3:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-4:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via4:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-5:	areacap=0.0843FF/um^2,	edgecap=0.0974FF/um,	res=0.078ohms/sq
***    Via5:	areacap=0.0FF/um^2,	edgecap=0.0FF/um,	res=0.8ohms/sq
***    Metal-6:	areacap=0.0423FF/um^2,	edgecap=0.1273FF/um,	res=0.036ohms/sq
.OPTIONS NOMOD NOPAGE

*** CELL: Inv_20_10{lay}
.SUBCKT Inv_20_10 In Out gnd vdd
Mnmos@0 Out In#1 gnd gnd NMOS L=0.6U W=3U
Mpmos@0 Out In#3 vdd vdd PMOS L=0.6U W=6U
** Extracted Parasitic Capacitors ***
C0 In 0 0.11fF
C1 Out 0 2.13fF
C2 vdd 0 0.54fF
C3 In#0 0 0.15fF
C4 In#4 0 0.29fF
C5 In#3 0 0.1fF
** Extracted Parasitic Resistors ***
R0 In#0 In#0##0 5.425
C6 In#0##0 0 0.073fF
R1 In#0##0 In#1 5.425
R2 In#3 In#3##0 6.717
C7 In#3##0 0 0.102fF
R3 In#3##0 In#3##1 6.717
C8 In#3##1 0 0.102fF
R4 In#3##1 In#4 6.717
R5 In#4 In#4##0 5.425
C9 In#4##0 0 0.073fF
R6 In#4##0 In#0 5.425
R7 In In##0 7.492
C10 In##0 0 0.114fF
R8 In##0 In##1 7.492
C11 In##1 0 0.114fF
R9 In##1 In#4 7.492
.ENDS Inv_20_10

*** TOP LEVEL CELL: inv_sim{lay}
XInv_20_1@1 In Out GND VDD Inv_20_10
** Extracted Parasitic Capacitors ***
C0 GND 0 3.04fF
C1 In 0 1.88fF
C2 Out 0 1.9fF
C3 VDD 0 2.4fF
** Extracted Parasitic Resistors ***

* Spice Code nodes in cell cell 'inv_sim{lay}'
VDD VDD 0 DC 5
VGND GND 0 DC 0
Vin in 0 DC 0
.include C:\Electric\C5_models.txt
.options post
.DC Vin 0 5 1mV
.END