*** SPICE deck for cell inv_sim{sch} from library CMOSedu_3
*** Created on Tue May 22, 2007 16:43:54
*** Last revised on Tue May 22, 2007 17:04:24
*** Written on Wed May 23, 2007 09:34:21 by Electric VLSI Design System, 
*version 8.05l
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.OPTIONS NOMOD NOPAGE

*** CELL: Inv_20_10{sch}
.SUBCKT Inv_20_10 In Out gnd vdd
** GLOBAL gnd
** GLOBAL vdd
Mnmos@0 Out In gnd gnd NMOS L=0.6U W=3U
Mpmos@0 vdd In Out vdd PMOS L=0.6U W=6U
.ENDS Inv_20_10

*** TOP LEVEL CELL: inv_sim{sch}
XInv_20_1@0 In Out gnd vdd Inv_20_10

* Spice Code nodes in cell cell 'inv_sim{sch}'
VDD VDD 0 DC 5
VGND GND 0 DC 0
Vin in 0 DC 0
.include C:\Electric\C5_models.txt
.options post
.DC Vin 0 5 1mV
.END