# header information: HCMOSedu_2|8.05l # Views: Vicon|ic Vschematic|sch # Technologies: Tmocmos|ScaleFORmocmos()D300.0|mocmosNumberOfMetalLayers()I3 # Cell Inv_20_10;1{ic} CInv_20_10;1{ic}||artwork|1179874258531|1179875021296|E Ngeneric:Facet-Center|art@0||0|0|0|0||AV NOpened-Polygon|art@3||5.25|0|6|6|||trace()V[-3/-3,-3/3,3/0,-3/-3] NCircle|art@4||8.75|0|1|1|| Nschematic:Bus_Pin|pin@0||0.25|0|2|2|| Nschematic:Wire_Pin|pin@1||2.25|0|0.5|0.5|| Nschematic:Wire_Pin|pin@4||9.25|0|0.5|0.5|| Nschematic:Wire_Pin|pin@5||11|0|0.5|0.5|| Aschematic:wire|net@0||0|0|pin@1||2.25|0|pin@0||0.25|0 Aschematic:wire|net@2||0|1800|pin@4||9.25|0|pin@5||11|0 EIn||D5G2;X-1;|pin@0||U EOut||D5G2;X1.75;|pin@5||U X # Cell Inv_20_10;1{sch} CInv_20_10;1{sch}||schematic|1179859020546|1179875041406| IInv_20_10;1{ic}|Inv_20_1@0||1|14.75|||D5G4; Ngeneric:Facet-Center|art@0||0|0|0|0||AV NOff-Page|conn@0||-3.75|1|4|2|| NOff-Page|conn@1||8|1|4|2|| NGround|gnd@0||3.75|-6.75|3|4|| NTransistor|nmos@0||1.75|-1.75|4|3|R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-1.5;)SNMOS NWire_Pin|pin@0||0|3.75|0.5|0.5|| NWire_Pin|pin@1||0|-1.75|0.5|0.5|| NWire_Pin|pin@3||0|1|0.5|0.5|| NWire_Pin|pin@6||3.75|1|0.5|0.5|| NTransistor|pmos@0||1.75|3.75|4|3|R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-1.5;)SPMOS NPower|pwr@0||3.75|8.25|3|3|| Awire|net@0||0|900|nmos@0|s|3.75|-3.75|gnd@0||3.75|-4.75 Awire|net@2||0|2700|pmos@0|d|3.75|5.75|pwr@0||3.75|8.25 Awire|net@3||0|0|pmos@0|g|0.75|3.75|pin@0||0|3.75 Awire|net@5||0|1800|pin@1||0|-1.75|nmos@0|g|0.75|-1.75 Awire|net@7||0|900|pin@0||0|3.75|pin@3||0|1 Awire|net@11||0|900|pin@3||0|1|pin@1||0|-1.75 Awire|net@12||0|900|pmos@0|s|3.75|1.75|pin@6||3.75|1 Awire|net@13||0|0|conn@1|a|6|1|pin@6||3.75|1 Awire|net@14||0|900|pin@6||3.75|1|nmos@0|d|3.75|0.25 Awire|net@16||0|0|pin@3||0|1|conn@0|y|-1.75|1 EIn||D5G2;X-1;|conn@0|a|U EOut||D5G2;X1.75;|conn@1|y|U X # Cell inv_sim;1{sch} Cinv_sim;1{sch}||schematic|1179873834703|1179875064328| IInv_20_10;1{ic}|Inv_20_1@0||5.5|5|||D5G4; Ngeneric:Facet-Center|art@0||0|0|0|0||AV Ngeneric:Invisible-Pin|pin@0||9.25|11.25|0|0|||SIM_spice_card(D5G0.5;)S[VDD VDD 0 DC 5,VGND GND 0 DC 0,Vin in 0 DC 0,".include C:\\Electric\\C5_models.txt",.options post,.DC Vin 0 5 1mV] NWire_Pin|pin@3||2|5|0.5|0.5|| NWire_Pin|pin@4||18.25|5|0.5|0.5|| Awire|In|D5G1;X-0.5;Y0.5;|0|0|Inv_20_1@0|In|5.75|5|pin@3||2|5 Awire|Out|D5G1;Y0.5;|0|1800|Inv_20_1@0|Out|16.5|5|pin@4||18.25|5 X # Groups: GInv_20_10;1{sch}|Inv_20_10;1{ic} Ginv_sim;1{sch}