PDC+KD1S Chip

Photon detection circuits & KD1S ADC

Contributors

Gonzalo Arteaga (arteag1@unlv.nevada.edu)

Shada Sharif (sharifs@unlv.nevada.edu)

Chip Organization

The chip was designed using AMS 0.35-µm SiGe BiCMOS process in 2018. The chip measures 2-mm x 2-mm and contains the following circuits:

1) KD1S noise-shaping analog-to-digital converter

2) Photon detection circuits

a. 8 x 8 Pixel array each consisting of a 25-µm x 25-µm avalanche photodiode (APD), passive/active-quenching circuit, monostable pulse-shortening circuit (for passive-quenching only), and an analog counter

b. Standalone APD + passive-quenching circuit and APD + active-quenching circuit

c. Standalone analog counter

Figure 1: Layout view of the chip with the metal fill omitted.